This week Samsung Electronics and Synopsys announced that Samsung has taped out its first mobile system-on-chip on Samsung Foundry's 3nm gate-all-around (GAA) process technology. The announcement, coming from electronic design automation Synopsys, further notes that Samsung used the Synopsys.ai EDA suite to place-n-route the layout and verify design of the SoC, which in turn enabled higher performance.

Samsung's unnamed high-performance mobile SoC relies on 'flagship' general-purpose CPU and GPU architectures as well as various IP blocks from Synopsys. SoC designers used Synopsys.ai EDA software, including the Synopsys DSO.ai to fine-tune design and maximize yields as well as Synopsys Fusion Compiler RTL-to-GDSII solution to achieve higher performance, lower power, and optimize area (PPA).

And while the news that Samsung has developed a high-performance SoC using the Synopsys.ai suite is important, there is another, even more important dimension to this announcement: this means that Samsung has finally taped out an advanced smartphone application processor on its cutting-edge 3nm GAAFET process.

Although Samsung Foundry has been producing chips on its GAA-equipped SF3E (3 nm-class, 'early' node) process for almost two years now, Samsung Electronics has never used this technology for its own system-on-chips for smartphones or other complex devices. To date, SF3E has been used mainly for cryptocurrency mining chips, presumably due to the inevitable early teething and yield issues that come with being the industry's first commercial GAAFET process.

For now, Samsung isn't disclosing what specific process node is being used for the SoC; the official Samsung/Synposys announcement only notes that it's for a GAA process node. Along with their first-generation 3nm-class SF3E, Samsung Foundry has a considerably more sophisticated SF3 manufacturing technology that offers numerous improvements over SF3E, and is due to be used for mass production in the coming quarters. Given the timing of the announcement, the reasonable bet is that they're using SF3.

As for Samsung's tooling partnership with Synopsys, the latter's tools are being credited for delivering some significant performance improvements to the chip's design. In particular, the two firms are crediting those tools for improving the chip's peak clockspeed by 300MHz while cutting down on dynamic power usage by 10%. To accomplish that, Samsung Electronics' SoC developers used design partitioning optimization, multi-source clock tree synthesis (MSCTS), and smart wire optimization to reduce signal interference, along with a simpler hierarchical approach. And by using Synopsys Fusion Compiler, they did all this while being able to skip weeks of 'manual' design work, according to the joint press release.

"Our longstanding collaboration has delivered leading-edge SoC designs," said Kijoon Hong, vice president of SLSI at Samsung Electronics. "This is a remarkable milestone to successfully achieve the highest performance, power and area on the most advanced mobile CPU cores and SoC designs in collaboration with Synopsys. Not only have we demonstrated that AI-driven solutions can help us achieve PPA targets for even the most advanced GAA process technologies, but through our partnership we have established an ultra-high-productivity design system that is consistently delivering impressive results."

As part of Samsung's Q1 earnings announcement, the company has outlined some of its foundry unit's key plans for the rest of the year. The company has confirmed that it remains on track to meeting its goal of starting mass production of chips on its SF3 (3 nm-class, 2nd Generation) technology in the second half of the year. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) process technology, which will offer a mix of performance and efficiency enhancements. Finally, the company the company is preparing a variation of its 4 nm-class technology for integration into stacked 3D designs.

SF2 To Be Unveiled In June

Samsung plans to disclose key details about its SF2 fabrication technology at the VLSI Symposium 2024 on June 19. This will be the company's second major process node based upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will feature a 'unique epitaxial and integration process,' which will give the process node higher performance and lower leakage than traditional FinFET-based nodes (though Samsung isn't disclosing the specific node they're comparing it to).

Samsung says that SF2 increases performance of narrow transistors by 29% for N-type and 46% for P-type, and wide transistors by 11% and 23% respectively. Moreover, it reduces transistor global variation by 26% compared to FinFET technology, and cuts product leakage by approximately 50%. This process also sets the stage for future advancements in technology through enhanced design technology co-optimization (DTCO) collaboration with its customers.

One thing that Samsung has not mentioned in context of SF2 is backside power delivery, so at least for the moment, there is no indication that Samsung will be adopting this next-gen power routing feature for SF2.

Samsung says that the design infrastructure for SF2 – the PDK, EDA tools, and licensed IP – will be finalized in the second quarter of 2024. Once this happens, Samsung's chip development partners will be able to begin designing products for this production node. Meanwhile, Samsung is already working with Arm to co-optimize Arm's Cortex cores for the SF2 process.

SF3: On Track for 2H 2024

As the first fab to introduce a GAAFET-based node, Samsung has been on the cutting edge of chip construction. At the same time, however, that has also meant that they're the first fab to encounter and solve the inevitable teething issues that come with such a major transistor design change. Consequently, while Samsung's first-generation SF3E process technology has been in production for a little less than two years now, the only publicly-disclosed chips made on the process so far have been relatively small cryptocurrency mining chips – exactly the kind of pipecleaner parts that do well on a new process node.

But with that experience in hand, Samsung is preparing to move on to making bigger and better chips with GAAFETs. As part of their earnings announcements, the company has confirmed that their updated SF3 node, which was introduced last year, remains on schedule to enter production in the second half of 2024.

A more mature product from the get-go, SF3 is being prepared to be used for building larger processors, including datacenter products. Compared to its direct predecessor, SF4, SF3 promises a 22% performance boost at the same power and transistor count, or a 34% lower power at the same frequency and complexity, as well as a 21% logic area reduction. In general, Samsung pins a lot of hopes on this technology, as it's this generation of their 3nm-class technology that is poised to compete against TSMC's N3B and N3E nodes.

SF4: Ready for 3D Stacking

Finally, Samsung is also preparing a variant of their final FinFET technology node, SF4, for use in 3D chiplet stacking. As transistor density improvements have continued to slow, 3D chip stacking has emerged as a way to keep boosting overall chip performance, especially with modern, multi-tile processor designs.

Details on this node are limited, but it would seem that Samsung is making some changes to account/optimize for using SF4-fabbed chiplets in a 3D-stacked design, where chips need to be able to communicate both up and down. According to the company's Q1 financial report, Samsung expects to complete their preparatory work on the chip-stacking SF4 variant during the current quarter (Q2).

Sources: Samsung, Samsung

TSMC is no stranger to building big chips. Besides the ~800mm2 reticle limit of their normal logic processes, the company already produces even larger chips by fitting multiple dies on to a single silicon interposer, using their chip-on-wafer-on-substrate (CoWoS) technology. But even with current-gen CoWoS allowing for interposers up to 3.3x TSMC's reticle limit, TSMC plans to build bigger still in response to projected demand from the HPC and AI industries. To that end, as part of the company's North American Technology Symposium last week, TSMC announced that they are developing the means of building super-sized interposers that can reach over 8x the reticle limit.

TSMC's current-generation CoWoS technology allows for building interposers up to 2831 mm² and the company is already seeing customers come in with designs that run up to those limits. Both AMD's Instinct MI300X accelerator and NVIDIA's forthcoming B200 accelerator are prime examples of this, as they pack huge logic chiplets (3D stacked in case of AMD's product) and eight HBM3/HBM3E memory stacks in total. The total space afforded by the interposer gives these processors formidable performance, but chip developers want to go more powerful still. And to get there as quickly as possible, they'll need to go bigger as well in order to incorporate more logic chiplets and more memory stacks.

For their next-generation CoWoS product that's set to launch in 2026, TSMC plans to release CoWoS_L, which will offer a maximum interposer size of approximately 5.5 times that of a photomask, totaling 4719 mm² altogether. This next generation package will support up to 12 HBM memory stacks and will necessitate a larger substrate measuring at 100×100 mm. Coupled with process node improvements over the next few years, and TSMC expects chips based on this generation of CoWoS to offer better than 3.5x the compute performance of current-generation CoWoS chips.

Farther down the line, in 2027 TSMC intends introduce a version of CoWoS that allows for interposers up to 8 times larger than the reticle limit. This will offer an ample 6,864 mm² of space for chiplets on a substrate that measures 120×120 mm. TSMC envisions leveraging this technology for designs that integrate four stacked systems-on-integrated chips (SoICs), with 12 HBM4 memory stacks and extra I/O dies. TSMC roughly projects that this will enable chip designers to once again double performance, producing chips that surpass 7x the performance of current-generation chips.

Of course, building such large chips will come with its own set of consequences, above and beyond what TSMC will have to deal with. Enabling chip designers to build such grand processors is going to impact system design, as well as how datacenters accommodate these systems. TSMC's 100×100mm substrate will be riding right up to the limit of the OAM 2.0 form factor, whose modules measure 102×165mm to begin with. And if that generation of CoWoS doesn't break the current OAM form factor, then 120×120mm chips certainly will. And, of course, all of that extra silicon requires additional power and cooling, which is why we're already seeing hardware vendors prepare for how to cool multi-kilowatt chips by investigating liquid and immersion cooling.

Ultimately, even if Moore's Law has slowed to a crawl in terms of delivering transistor density improvements, CoWoS offers an out for producing chips with an ever-larger number of transistors. So with TSMC set to offer interposers and substrates with over twice the area of today's solutions, big chips intended for HPC systems are only going to continue to grow in both performance and size.

Related Reading

• TSMC's 1.6nm Technology Announced for Late 2026: A16 with "Super Power Rail" Backside Power
• TSMC 2nm Update: N2 In 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells
• TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction
• TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips
• TSMC Jumps Into Silicon Photonics, Lays Out Roadmap For 12.8 Tbps COUPE On-Package Interconnect

Optical connectivity – and especially silicon photonics – is expected to become a crucial technology to enable connectivity for next-generation datacenters, particularly those designed HPC applications. With ever-increasing bandwidth requirements needed to keep up with (and keep scaling out) system performance, copper signaling alone won't be enough to keep up. To that end, several companies are developing silicon photonics solutions, including fab providers like TSMC, who this week outlined its 3D Optical Engine roadmap as part of its 2024 North American Technology Symposium, laying out its plan to bring up to 12.8 Tbps optical connectivity to TSMC-fabbed processors.

TSMC's Compact Universal Photonic Engine (COUPE) stacks an electronics integrated circuit on photonic integrated circuit (EIC-on-PIC) using the company's SoIC-X packaging technology. The foundry says that usage of its SoIC-X enables the lowest impedance at the die-to-die interface and therefore the highest energy efficiency. The EIC itself is produced at a 65nm-class process technology.

TSMC's 1st Generation 3D Optical Engine (or COUPE) will be integrated into an OSFP pluggable device running at 1.6 Tbps. That's a transfer rate well ahead of current copper Ethernet standards – which top out at 800 Gbps – underscoring the immediate bandwidth advantage of optical interconnects for heavily-networked compute clusters, never mind the expected power savings.

Looking further ahead, the 2nd Generation of COUPE is designed to integrate into CoWoS packaging as co-packaged optics with a switch, allowing optical interconnections to be brought to the motherboard level. This version COUPE will support data transfer rates of up to 6.40 Tbps with reduced latency compared to the first version.

TSMC's third iteration of COUPE – COUPE running on a CoWoS interposer – is projected to improve on things one step further, increasing transfer rates to 12.8 Tbps while bringing optical connectivity even closer to the processor itself. At present, COUPE-on-CoWoS is in the pathfinding stage of development and TSMC does not have a target date set.

Ultimately, unlike many of its industry peers, TSMC has not participated in the silicon photonics market up until now, leaving this to players like GlobalFoundries. But with its 3D Optical Engine Strategy, the company will enter this important market as it looks to make up for lost time.

Related Reading

• TSMC's 1.6nm Technology Announced for Late 2026: A16 with "Super Power Rail" Backside Power
• TSMC 2nm Update: N2 In 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells
• TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction
• TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips

TSMC has been offering its System-on-Wafer integration technology, InFO-SoW, since 2020. For now, only Cerebras and Tesla have developed wafer scale processor designs using it, as while they have fantastic performance and power efficiency, wafer-scale processors are extremely complex to develop and produce. But TSMC believes that not only will wafer-scale designs ramp up in usage, but that megatrends like AI and HPC will call for even more complex solutions: vertically stacked system-on-wafer designs.

Tesla Dojo's wafer-scale processors — the first solutions based based on TSMC's InFO-SoW technology that are in mass production — have a number of benefits over typical system-in-packages (SiPs), including low-latency high-bandwidth core-to-core communications, very high performance and bandwidth density, relatively low power delivery network impendance, high performance efficiency, and redunancy.

But with InFO-SoW and other wafer scale integration methods, processor designers have to rely solely on on-chip memory. This is perfectly adequate for many applications, but it may not be enough for next-generation AI workloads. Furthermore, with InFO-SoW, the whole wafer has to be processed using one fabrication technology, which may not be optimal, or too expensive for certain designs.

So, with its next-generation system-on-wafer platform, TSMC plans to bring together two of its packaging technologies: InFO-SoW and System on Integrated Chips (SoIC), which will allow it to stack memory or logic on top of a system-on-wafer using its Chip-on-Wafer (CoW) method. The CoW-SoW technology, which the company announced at its North American Technology Symposium, will be ready for mass production in 2027.

For now, TSMC is mostly talking about wedding wafer scale processors with HBM4 memory. And given that HBM4 stacks will feature a 2048-bit interface, its tighter integration with logic is something that the industry is considering.

"So, in the future, using wafer level integrations [will allow] our customers to integrate even more logic and memory together," said Kevin Zhang, Vice President of Business Development at TSMC. "SoW is no longer a fiction, this is something we already work with our customers [on] to produce some of the products already in place. This we think by leveraging our advanced wafer level integration technology, we can provide our customer a very important the path allow them to continue to grow their capability to bring in more computation, more energy efficient computation, to their AI cluster or [supercomputer]."

Related Reading

• TSMC's 1.6nm Technology Announced for Late 2026: A16 with "Super Power Rail" Backside Power
• TSMC 2nm Update: N2 In 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells
• TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction

While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature and proven process technologies for years to come. Which is why TSMC has continued to refine its existing nodes, including its current-generation 5nm-class offerings. To that end, at its North American Technology Symposium 2024, the company introduced a new, optimized 5nm-class node: N4C.

TSMC's N4C process belongs to the company's 5nm-class family of fab nodes and is a superset of N4P, the most advanced technology in that family. In a bid to further bring down 5nm manufacturing costs, for TSMC is implementing several changes for N4C, including rearchitecting their standard cell and SRAM cell, changing some design rules, and reducing the number of masking layers. As a result of these improvements, the company expects N4C to achieve both smaller die sizes as well as a reduction in production complexity, which in turn will bring die costs down by up to 8.5%. Furthermore, with the same wafer-level defect density rate as N4P, N4C stands to offer even higher functional yields thanks to its die area reduction.

"So, we are not done with our 5nm and 4nm [technologies]," said Kevin Zhang, Vice President of Business Development at TSMC. "From N5 to N4, we have achieved 4% density improvement optical shrink, and we continue to enhance the transistor performance. Now we bring in N4C to our 4 nm technology portfolio. N4C allows our customers to reduce their costs by remove some of the masks and to also improve on the original IP design like a standard cell and SRAM to further reduce the overall product level cost of ownership."

TSMC says that N4C can use the same design infrastructure as N4P, though it is unclear whether N5 and N4P IP can be re-used for N4C-based chips. Meanwhile, TSMC indicates that it offers various options for chipmakers to find the right balance between cost benefits and design effort, so companies interested in adopting a 4nm-class process technologies could well adopt N4C.

The development of N4C comes as many of TSMC's chip design customers are preparing to launch chips based on the company's final generation of FinFET process technology, the 3nm N3 series. While N3 is expected to be a successful family, the high costs of N3B have been an issue, and the generation is marked by diminishing performance and transistor density returns altogether. Consequently, N4C could well become a major, long-lived node at TSMC, serving as a good fit for customers who want to stick to a more cost-effective FinFET node.

"This is a very significant enhancement, we are working with our customer, basically to extract more value from their 4 nm investment," Zhang said.

TSMC expects to start volume production of N4C chips some time next year. And with TSMC having produced 5nm-class for nearly half a decade at that point, N4C should be able to hit the ground running in terms of volume and yields.

Related Reading

• TSMC's 1.6nm Technology Announced for Late 2026: A16 with "Super Power Rail" Backside Power
• TSMC 2nm Update: N2 In 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells
• TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips
• TSMC Jumps Into Silicon Photonics, Lays Out Roadmap For 12.8 Tbps COUPE On-Package Interconnect

Taiwan Semiconductor Manufacturing Co. provided several important updates about its upcoming process technologies at its North American Technology Symposium 2024. At a high level, TSMC's 2 nm plans remain largely unchanged: the company is on track to start volume production of chips on it's first-generation GAAFET N2 node in the second half of 2025, and N2P will succeed N2 in late 2026 – albeit without the previously-announced backside power delivery capabilities. Meanwhile, the whole N2 family will be adding TSMC's new NanoFlex capability, which allows chip designers to mix and match cells from different libraries to optimize performance, power, and area (PPA). 

One of the key announcements of the event is TSMC's NanoFlex technology, which will be a part of the company's complete N2 family of production nodes (2 nm-class, N2, N2P, N2X). NanoFlex will enable chip designers to mix and match cells from different libraries (high performance, low power, area efficient) within the same block design, allowing designers to fine tune their chip designs to improve performance or lower power consumption.

TSMC's contemporary N3 fabrication process already supports a similar capability called FinFlex, which also allows designers to use cells from different libraries. But since N2 relies on gate-all-around (GAAFET) nanosheet transistors, NanoFlex gives TSMC some additional controls: firstly, TSMC can optimize channel width for performance and power and then build short cells (for area and power efficiency) or tall cells (for up to 15% higher performance).  

When it comes to timing, TSMC's N2 is set to enter risk production in 2025 and high-volume manufacturing (HVM) in the second half of 2025, so it looks like we are going to see N2 chips in retail devices in 2026. Compared to N3E, TSMC expects N2 to increase performance by 10% to 15% at the same power, or reduce power consumption by 25% to 30% at the same frequency and complexity. As for chip density, the foundry is looking at a 15% density increase, which is a good degree of scaling by contemporary standards.

N2 will be followed by performance-enhanced N2P, as well as the voltage-enhanced N2X in 2026. Although TSMC once said that N2P would add backside power delivery network (BSPDN) in 2026, it looks like this will not be the case and N2P will use regular power delivery circuitry. The reason for this is unclear, but it looks like the company decided not to add a costly feature to N2P, but to reserve it to its next-generation node, which will also be available to customers in late 2026.

N2 is still expected to feature a major innovation related to power: super-high-performance metal-insulator-metal (SHPMIM) capacitors, which are are being added to improve power supply stability. The SHPMIM capacitor offers more than twice the capacity density of TSMC's existing super-high-density metal-insulator-metal (SHDMIM) capacitor. Additionally, the new SHPMIM capacitor cuts sheet resistance (Rs in Ohm/square) and via resistance (Rc) by 50% compared to its predecessor.

Related Reading

• TSMC's 1.6nm Technology Announced for Late 2026: A16 with "Super Power Rail" Backside Power
• TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction
• TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips
• TSMC Jumps Into Silicon Photonics, Lays Out Roadmap For 12.8 Tbps COUPE On-Package Interconnect

With the arrival of spring comes showers, flowers, and in the technology industry, TSMC's annual technology symposium series. With customers spread all around the world, the Taiwanese pure play foundry has adopted an interesting strategy for updating its customers on its fab plans, holding a series of symposiums from Silicon Valley to Shanghai. Kicking off the series every year – and giving us our first real look at TSMC's updated foundry plans for the coming years – is the Santa Clara stop, where yesterday the company has detailed several new technologies, ranging from more advanced lithography processes to massive, wafer-scale chip packing options.

Today we're publishing several stories based on TSMC's different offerings, starting with TSMC's marquee announcement: their A16 process node. Meanwhile, for the rest of our symposium stories, please be sure to check out the related reading below, and check back for additional stories.

• TSMC's 1.6nm Technology Announced for Late 2026: A16 with "Super Power Rail" Backside Power
• TSMC 2nm Update: N2 In 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells
• TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction
• TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips
• TSMC Jumps Into Silicon Photonics, Lays Out Roadmap For 12.8 Tbps COUPE On-Package Interconnect
• TSMC Readies 8x Reticle Super Carrier Interposer For Next-Gen Chips Twice as Large As Today's

Headlining its Silicon Valley stop, TSMC announced its first 'angstrom-class' process technology: A16. Following a production schedule shift that has seen backside power delivery network technology (BSPDN) removed from TSMC's N2P node, the new 1.6nm-class production node will now be the first process to introduce BSPDN to TSMC's chipmaking repertoire. With the addition of backside power capabilities and other improvements, TSMC expects A16 to offer significantly improved performance and energy efficiency compared to TSMC's N2P fabrication process. It will be available to TSMC's clients starting H2 2026.

TSMC A16: Combining GAAFET With Backside Power Delivery

At a high level, TSMC's A16 process technology will rely on gate-all-around (GAAFET) nanosheet transistors and will feature a backside power rail, which will both improve power delivery and moderately increase transistor density. Compared to TSMC's N2P fabrication process, A16 is expected to offer a performance improvement of 8% to 10% at the same voltage and complexity, or a 15% to 20% reduction in power consumption at the same frequency and transistor count. TSMC is not listing detailed density parameters this far out, but the company says that chip density will increase by 1.07x to 1.10x – keeping in mind that transistor density heavily depends on the type and libraries of transistors used.

The key innovation of TSMC's A16 node, is its Super Power Rail (SPR) backside power delivery network, a first for TSMC. The contract chipmaker claims that A16's SPR is specifically tailored for high-performance computing products that feature both complex signal routes and dense power circuitry.

As noted earlier, with this week's announcement, A16 has now become the launch vehicle for backside power delivery at TSMC. The company was initially slated to offer BSPDN technology with N2P in 2026, but for reasons that aren't entirely clear, the tech has been punted from N2P and moved to A16. TSMC's official timing for N2P in 2023 was always a bit loose, so it's hard to say if this represents much of a practical delay for BSPDN at TSMC. But at the same time, it's important to underscore that A16 isn't just N2P renamed, but rather it will be a distinct technology from N2P.

TSMC is not the only fab pursuing backside power delivery, and accordingly, we're seeing multiple variations on the technique crop up at different fabs. The overall industry has three approaches for BSPDN: Imec's Buried Power Rail, Intel's PowerVia, and now TSMC's Super Power Rail.

The oldest technique, Imec's Buried Power Rail, essentially places power delivery network on the backside of the wafer and then connects power rail of logic cells to power contact using nano TSVs. This enables some area scaling and does not add too much complexity to production. The second implementation, Intel's PowerVia, connects power to the cell or transistor contact, which provides a better result, but at the cost of complexity.

Finally, we have TSMC's new Super Power Rail BSPDN technology, which connects a backside power network directly to each transistor's source and drain. According to TSMC, this is the most efficient technology in terms of area scaling, but the trade-off is that it's the most complex (and expensive) when it comes to production.

That TSMC has opted to go with the most complex version of BSPDN may be part of the reason that we've seen it removed from N2P, as implementing it will ultimately add to both time and costs. This leaves A16 as TSMC's premiere performance node for the 2026/2027 time-frame, while N2P can be positioned to offer a more balanced combination of performance and cost efficiency.

Angstrom Era Kicks Off In Late 2026 With New Node Naming Convention

Finally, as with Intel, we're also seeing TSMC adopt a new process node naming convention starting with this generation of technology. The name itself is largely arbitrary – and this has already been the case in the fab industry for several years now – but with current node names already in the single digits (e.g. N2), the industry has needed to re-calibrate node names to something smaller than the nanometer. And thus we've arrived at the 'angstrom era.' But regardless of what exactly it's called or why it's called that, the important point is that A16 will be the next generation node beyond TSMC's 2nm-class products.

TSMC expects to start volume production on A16 in H2 2026, so it is likely that the first products based on this technology will hit the market in 2027. Given the timing, the production node will presumably compete against Intel's 14A; though at 2+ years out and with no one producing BSPDN in volume today, there's still a lot of time for plans and roadmaps to change.

Taiwan Semiconductor Manufacturing Co. this week released its financial results for Q1 2024. Due to a rebound in demand for semiconductors, the company garned $18.87 billion in revenue for the quarter, which is up 12.9% year-over-year, but a decline of 3.8% quarter-over-quarter. The company says that in increase in demand for HPC processors (which includes processors for AI, PCs, and servers) drove its revenue rebound in Q1, but surprisingly, revenue share of TSMC's flagship N3 (3nm-class) process technology declined steeply quarter-over-quarter.

"Our business in the first quarter was impacted by smartphone seasonality, partially offset by continued HPC-related demand," said Wendell Huang, senior VP and chief financial officer of TSMC. "Moving into second quarter 2024, we expect our business to be supported by strong demand for our industry-leading 3nm and 5nm technologies, partially offset by continued smartphone seasonality."

In the first quarter of 2024, N3 wafer sales accounted for 9% of the foundry's revenue, down from 15% in Q4 2023, and up from 6% in Q3 2023. In terms of dollars, TSMC's 3nm production brought in around $1.698 billion, which is lower than $2.943 billion in the previous quarter. Meanwhile, TSMC's other advanced process technologies increased their revenue share: N5 (5 nm-class) accounted for 37% (up from 35%), and N7 (7 nm-class) commanded 19% (up from 17%). Though both remained relatively flat in terms of revenue, at $6.981 billion and $3.585 billion, respectively.

Generally, advanced technology nodes (N7, N5, N3) generated 65% of TSMC's revenue (down 2% from Q4 2023), while the broader category of FinFET-based process technologies contributed 74% to the company's total wafer revenue (down 1% from the previous quarter).

TSMC itself attributes the steep decline of N3's contribution to seasonally lower demand for smartphones in the first quarter as compared to the fourth quarter, which may indeed be the case as demand for iPhones typically slowdowns in Q1. Along those lines, there have also been reports about a drop in demand for the latest iPhones in China.

But even if A17 Pro production volumes are down, Apple remains TSMC's lead customer for N3B, as the fab also produces their M3, M3 Pro, and M3 Max processors on the same node. These SoCs are larger in terms of die sizes and resulting costs, so their contribution to TSMC's revenue should be quite substantial.

"Moving on to revenue contribution by platform. HPC increased 3% quarter-over-quarter to account for 46% of our first quarter revenue," said Huang. "Smartphone decreased 16% to account for 38%. IoT increased 5% to account for 6%. Automotive remained flat and accounted for 6%, and DCE increased 33% to account for 2%."

Meanwhile, as demand for AI and HPC processors will continue to increase in the coming years, TSMC expects its HPC platform to keep increasing its share in its revenue going forward.

"We expect several AI processors to be the strongest driver of our HPC platform growth and the largest contributor in terms of our overall incremental revenue growth in the next several years," said C.C. Wei, chief executive of TSMC.

This week ASML is making two very important announcements related to their progress with high numerical aperature extreme ultraviolet lithography (High-NA EUV). First up, the company's High-NA EUV prototype system at its fab in Veldhoven, the Netherlands, has printed the first 10nm patterns, which is a major milestone for ASML and their next-gen tools. Second, the company has also revealed that it's second High-NA EUV system is now out the door as well, and has been shipped to an unnamed customer.

"Our High-NA EUV system in Veldhoven printed the first-ever 10 nanometer dense lines," a statement by ASML reads. "Imaging was done after optics, sensors and stages completed coarse calibration. Next up: bringing the system to full performance. And achieving the same results in the field."

Our High NA EUV system in Veldhoven printed the first-ever 10 nanometer dense lines. ✨ Imaging was done after optics, sensors and stages completed coarse calibration.

Next up: bringing the system to full performance. And achieving the same results in the field. ⚙️ pic.twitter.com/zcA5V0ScUf

— ASML (@ASMLcompany) April 17, 2024

Alongside the system shipped to Intel at the end of 2023, ASML has retained their own Twinscan EXE:5000 scanner at their Veldhoven, Netherlands, facility, which is what the company is using for further research and development into High-NA EUV. Using that machine, the company has been able to print dense lines spaced 10 nanometers apart, which is a major milestone in photolithography development. Previously, only small-scale, experimental lab machines have been able to achieve this kind of a resolution. Eventually, High-NA EUV tools will achieve a resolution of 8 nm, which will be instrumental to build logic chips on technologies beyond 3 nm.

Intel's Twinscan EXE:5000 scanner at its D1X fab near Hillsboro, Oregon is also close behind, and its assembly is said to be nearing completion. That machine will be primarily used for Intel's own High-NA EUV R&D, with Intel slated to use its successor — the commercial-grade Twinscan EXE:5200 — to produce its chips on its Intel 14A (1.4 nm-class) in mass quantities in 2026 – 2027.

But Intel will not be the only chipmaker that gets to experiment with a High-NA EUV scanner for very long. As revealed by ASML, the company recently started shipping another Twinscan EXE:5000 machine to yet another customer. The fab tool maker is not disclosing the client, but previously it has said that all of leading logic and memory producers are in the process of procuring High-NA tools for R&D purposes, so the list of 'suspects' is pretty short.

"Regarding High-NA, or 0.55 NA EUV, we shipped our first system to a customer and this system is currently under installation," said Christophe Fouquet, chief business officer of ASML, at the company's earnings conference call with analysts and investors. "We started to ship the second system this month and its installation is also about to start."

While Intel plans to adopt High-NA EUV tools ahead of the industry, other chipmakers seem to a bit more cautious and plan to rely on risky yet already known Low-NA EUV double patterning method for production a 3 nm and 2 nm. Still, regardless of the exact timing for a transition, all of the major fabs will be relying on High-NA EUV tools in due time. So all parties have an interest in how ASML's R&D turns out.

"The customer interest for our [High-NA] system lab is high as this system will help both our Logic and Memory customers prepare for High-NA insertion into their roadmaps," said Fouquet. "Relative to 0.33 NA, the 0.55 NA system provides finer resolution enabling an almost 3x increase in transistor density, at a similar productivity, in support of sub-2nm Logic and sub-10nm DRAM nodes."

Sources: ASML/X, ASML, Reuters

Samsung Electronics this week was awarded up to $6.4 billion from the U.S. government under the CHIPS and Science Act to build its new fab complex in Taylor, Texas. This is the third major award under the act in the last month, with all three leading-edge fabs – Intel, TSMC, and now Samsung – receiving multi-billion dollar funding packages under the domestic chip production program. Overall, the final price tag on Samsung's new fab complex is expected to reach $40 billion by the time it's completed later this decade.

Samsung's CHIPS Act funding was announced during a celebratory event attended by U.S. Secretary of Commerce Gina Raimondo and Samsung Semiconductor chief executive Kye Hyun Kyung.  During the event, Kyung outlined the strategic goals of the expansion, emphasizing that the additional funding will not only increase production capacity but also strengthen the entire local semiconductor ecosystem. Samsung plans to equip its fab near Taylor, Texas, with the latest wafer fab tools to produce advanced chips. The Financial Times reports that Samsung aims to produce semiconductors on its 2nm-class process technology starting 2026, though for now this is unofficial information.

"I am pleased to announce a preliminary agreement between Samsung and the Department of Commerce to bring Samsung's advanced semiconductor manufacturing and research and development to Texas," said Joe Biden, the U.S. president, in a statement. "This announcement will unleash over $40 billion in investment from Samsung, and cement central Texas's role as a state-of-the-art semiconductor ecosystem, creating at least 21,500 jobs and leveraging up to $40 million in CHIPS funding to train and develop the local workforce. These facilities will support the production of some of the most powerful chips in the world, which are essential to advanced technologies like artificial intelligence and will bolster U.S. national security."

Samsung has been a significant contributor to the Texas economy for decades, starting chip manufacturing in the U.S. in 1996. With previous investments totaling $18 billion in its Austin operations, Samsung's expansion into Taylor with an additional investment of at least $17 billion underscores its role as one of the largest foreign direct investors in U.S. history. The total expected investment in the new fab surpasses $40 billion, making it one of the largest for a greenfield project in the nation and transforming Taylor into a major hub for semiconductor manufacturing.

The CEO highlighted the substantial economic impact of Samsung's operations, noting a nearly double increase in regional economic output from $13.6 billion to $26.8 billion between 2022 and 2023. The ongoing expansion is projected to further stimulate economic growth, create thousands of jobs, and enhance the community's overall development.

“We are not just expanding production facilities; we’re strengthening the local semiconductor ecosystem and positioning the U.S. as a global semiconductor manufacturing destination.” said Kyung. “To meet the expected surge in demand from U.S. customers, for future products like AI chips, our fabs will be equipped for cutting-edge process technologies and help bring security to the U.S. semiconductor supply chain.”

Samsung is also committed to environmental sustainability and workforce development. The company plans to operate using 100% clean energy and incorporate advanced water management technologies. Additionally, it is investing in education and training programs to develop a new generation of semiconductor professionals. These initiatives include partnerships with educational institutions and programs tailored for military veterans.

In his remarks, Kyung expressed gratitude to President Biden, Secretary Raimondo, and other governmental and community supporters for their ongoing support. This collaborative effort between Samsung and various levels of government, as well as the local community, is pivotal in advancing America's semiconductor industry and ensuring its global competitiveness.

"Today’s announcement will help Samsung bring more semiconductor production, innovation, and jobs to U.S. shores, reinforcing America’s economy, competitiveness, and critical chip supply chains," a statememt by the Semiconductor Industry Associate reads. "We applaud Samsung for investing boldly in U.S.-based manufacturing and salute the U.S. Commerce Department for making significant headway in implementing the CHIPS Act’s manufacturing incentives and R&D programs. We look forward to continuing to work with leaders in government and industry to ensure the CHIPS Act remains on track to help reinvigorate U.S. chip manufacturing and research for many years to come."

TSMC has entered into a preliminary agreement with the U.S. Department of Commerce, securing up to $6.6 billion in direct funding and access to up to $5 billion in loans under the CHIPS and Science Act. With this latest round of support from the U.S. government, TSMC in turn will be adding a third fab to their Arizona project, with its investment in the region soaring to more than $65 billion. This move not only signifies the largest foreign direct investment in Arizona but also marks one of the biggest support packages that the U.S. government plans to make under the CHIPS Act, second only to Intel's $8.5 billion award last month.

TSMC is currently equipping its Fab 21 phase 1 and expects that it will start making chips using N4 and N5 (4 nm and 5 nm-class) process technologies in the first half of 2025. TSMC's Fab 21 phase 2 will commence operations in 2028, and will make chips on N3 and N2 (3 nm and 2 nm-class) production nodes. The newly-announced third fab (designation TBD) is set to manufacture chips on processes of 2 nm-class or beyond, with the start of production anticipated by the end of the decade.

TSMC has not announced a planned capacity for the new fab, only noting that it will be similar to the other two Arizona fabs, boasting a cleanroom space roughly twice as large as that of a typical "industry-standard logic fab." If it is sized similarly to the other Arizona fabs, then this strongly implies that the new fab will be another MegaFab-class facility – a mid-range fab producing around 25,000 wafer starts per month. TSMC does operate even larger fabs – the 100K WSPM GigaFab – though to date they've yet to build any of these outside of Taiwan.

“The CHIPS and Science Act provides TSMC the opportunity to make this unprecedented investment and to offer our foundry service of the most advanced manufacturing technologies in the United States,” said TSMC Chairman Dr. Mark Liu. “Our U.S. operations allow us to better support our U.S. customers, which include several of the world’s leading technology companies. Our U.S. operations will also expand our capability to trailblaze future advancements in semiconductor technology.”

The construction of three fabs in Arizona is poised to generate approximately 6,000 direct high-tech jobs, contributing significantly to the creation of a skilled workforce. This workforce is expected to play a crucial role in fostering a dynamic and competitive global semiconductor ecosystem. Moreover, the project is projected to create over 20,000 construction jobs, in addition to spawning tens of thousands of indirect jobs related to suppliers and consumer services.

AMD, Apple, and NVIDIA fully support TSMC's project and all of them expressed interest in using TSMC's capacities in the U.S.

“Today’s announcement highlights the strong commitment from Secretary Raimondo and the entire administration to ensure the U.S. plays a central role creating a more geographically diverse and resilient semiconductor supply chain,” said AMD Chair and CEO Lisa Su. “TSMC has a long track record of providing the leading-edge manufacturing capabilities that have enabled AMD to focus on what we do best, designing high-performance chips that change the world. We are committed to our partnership with TSMC and look forward to building our most advanced chips in U.S.”

TSMC's ventures in Arizona have encountered obstacles, such as setbacks caused by labor shortages and doubts about the U.S. governmental funding. As a result, production at the second facility has been postponed from 2026 to 2028. Moreover, Bloomberg has reported that at least one supplier for TSMC has called off its intended project in Arizona, attributing the decision to challenges in securing a workforce. The address the workforce issues, the TSMC grant includes a $50 million allocation for training of the local workforce.

Sources: TSMC, Bloomberg

Rapidus, a Japan-based company developing 2nm process technology and aiming to commercialize it in 2027, will receive a huge government grant for its ongoing projects. The Japanese government will support Rapidus with subsidies totaling ¥590 billion yen ($3.89 billion). In addition to developing its 2nm production node and spending on cleanroom equipment, Rapidus will also fund the development of multi-chiplet packaging technology.

This extra funding will significantly help the company's ambitious plans. With the government's total support now at ¥920 billion ($6.068 billion), Rapidus is getting a solid push to become a significant player in the semiconductor industry. The whole project is expected to cost around ¥5 trillion ($32.983 billion), so the funding is not quite there yet. Meanwhile, the company may get enough financing with support from the Japanese government and large Japanese conglomerates like Toyota Motor and Nippon Telegraph and Telephone.

According to Atsuyoshi Koike, Rapidus's chief executive, the company is on track to start testing its production by April 2025 and aims to begin large-scale production by 2027. Commercial production of 2nm chips is set to commence sometime in 2025.

In addition to developing its 2nm fabrication process in collaboration with IBM and building its manufacturing facility, Rapidus is also working on advanced packaging technology for multi-chiplet system-in-packages (SiPs). The latest government subsidies include more than ¥50 billion ($329.85 million) for research and development in this area, the first time Japan has provided subsidies for such technologies.

It is noteworthy that Rapidus will use a section of Seiko Epson Corporation's Chitose Plant (located in Chitose City, Hokkaido) for its back-end packaging processes. This plant is near the company's fab, which is currently being built in Bibi World, an industrial park in Chitose City. This space will be dedicated to pilot-stage research and development activities.

Sources: Rapidus, Nikkei

Intel and the United States Department of Commerce announced on Wednesday that they had inked a preliminary agreement under which Intel will receive $8.5 billion in direct funding under the CHIPS and Science Act. Furthermore, Intel is being made eligible for $11 billion in low-interest loans under the same law, and is being given access to a 25% investment tax credit on up to $100 billion of capital expenditures over the next five years. The funds from the long-awaited announcement will be used to expand or build new Intel's semiconductor manufacturing plants in Arizona, New Mexico, Ohio, and Oregon, potentially creating up to 30,000 jobs.

"Today is a defining moment for the U.S. and Intel as we work to power the next great chapter of American semiconductor innovation," said Intel CEO Pat Gelsinger. "AI is supercharging the digital revolution and everything digital needs semiconductors. CHIPS Act support will help to ensure that Intel and the U.S. stay at the forefront of the AI era as we build a resilient and sustainable semiconductor supply chain to power our nation's future."

Intel is working on several important projects, including new semiconductor production facilities and advanced packaging facilities. On the fab front, there are three ongoing projects: 

• Firstly, Intel is expanding its chip production capacities in Arizona — the Silicon Desert campus — by constructing two additional fab modules capable of making chips on Intel 18A and 20A production technologies at a projected cost of around $20 billion. 
• Secondly, the company is building its all-new Silicon Heartland campus in Licking County, near Columbus, Ohio. This extensive project is anticipated to require a total investment of $100 billion or more when fully developed, with an initial investment of around $20 billion for the first two fabrication modules, which are set to be completed in 2027 – 2028. 
• Thirdly, Intel is expanding and upgrading its chip production, research, and development capabilities in its Silicon Forest campus near Hillsboro, Oregon. In particular, the company recently began installing a $380 million High-NA EUV tool in its D1X fab in Oregon.

Regarding advanced packaging facilities, Intel is about to complete the conversion of two of its fabs in its Silicon Mesa campus in New Mexico to advanced packaging facilities. These facilities will be crucial to building next-generation multi-chipset processors for clients, data center, and AI applications in the coming years, and which will be the largest advanced packaging operation in the US. Meanwhile, with advanced packaging capacity in New Mexico already in place, the state is set to concentrate vast advanced packaging capabilities to support Intel's ramp of leading-edge fabs in Arizona, Ohio, and Oregon.

To receive both the $8.5 billion in direct funding and the $11 billion in low-interest, long-term loans, Intel must comply with the terms set in the so-called preliminary memorandum of terms (PMTs). The PMT specifies that receiving direct funding and federal loans will only be provided after thoroughly reviewing and negotiating detailed agreements. These financial awards also depend on meeting specific milestone goals, which are not public, but are thought to include terms concerning investments, timing, and workforce developments. Finally, all of this funding is subject to the availability of remaining CHIPS Act funds.

On top of this direct financial assistance, if Intel meets the U.S. government's requirements, it can also access a 25% tax credit on up to $100 billion of qualified capital expenditures over the next five years. This will make Intel's CapEx – the most expensive part of building and outfitting a chip fab – 'cheaper' for the company and stimulate it to invest in the U.S.

"With this agreement, we are helping to incentivize over $100 billion in investments from Intel – marking one of the largest investments ever in U.S. semiconductor manufacturing, which will create over 30,000 good-paying jobs and ignite the next generation of innovation," said U.S. Secretary of Commerce Gina Raimondo. "This announcement is the culmination of years of work by President Biden and bipartisan efforts in Congress to ensure that the leading-edge chips we need to secure our economic and national security are made in the U.S."

Last year, NVIDIA introduced its cuLitho software library, which promises to speed up photomask development by up to 40 times. Today, NVIDIA announced a partnership with TSMC and Synopsys to implement its computational lithography platform for production use, and use the company's next-generation Blackwell GPUs for AI and HPC applications.

The development of photomasks is a crucial step for every chip ever made, and NVIDIA's cuLitho platform, enhanced with new generative AI algorithms, significantly speeds up this process. NVIDIA says computational lithography consumes tens of billions of hours per year on CPUs. By leveraging GPU-accelerated computational lithography, cuLitho substantially improves over traditional CPU-based methods. For example, 350 NVIDIA H100 systems can now replace 40,000 CPU systems, resulting in faster production times, lower costs, and reduced space and power requirements.

NVIDIA claims its new generative AI algorithms provide an additional 2x speedup on the already accelerated processes enabled through cuLitho. This enhancement is particularly beneficial for the optical proximity correction (OPC) process, allowing the creation of near-perfect inverse masks to account for light diffraction.

TSMC says that integrating cuLitho into its workflow has resulted in a 45x speedup of curvilinear flows and an almost 60x improvement in Manhattan-style flows. Curvilinear flows involve mask shapes represented by curves, while Manhattan mask shapes are restricted to horizontal or vertical orientations.

Synopsys, a leading developer of electronic design automation (EDA), says that its Proteus mask synthesis software running on the NVIDIA cuLitho software library has accelerated computational workloads compared to current CPU-based methods. This acceleration is crucial for enabling angstrom-level scaling and reducing turnaround time in chip manufacturing.

The collaboration between NVIDIA, TSMC, and Synopsys represents a significant advancement in semiconductor manufacturing in general and cuLitho adoption in particular. By leveraging accelerated computing and generative AI, the partners are pushing semiconductor scaling possibilities and opening new innovation opportunities in chip designs.

Our avid readers tend to look at microelectronics made using leading edge process technologies, which in case of Intel means usage of High-NA extreme ultraviolet (EUV) lithography a couple of years down the road. But the vast majority of chips that we are going to use in the next couple of years will be made using Low-NA EUV litho tools. This is why the latest announcement from ASML is particularly notable.

As spotted by Computerbase, ASML this week has delivered its first updated Twinscan NXE:3800E lithography machine for fab installation. The latest iteration of the company's line of 0.33 numerical aperture (Low-NA) lithography scanners, the NXE:3800E is aimed at making chips on 2nm and 3nm-class technologies.

Chipmakers have a need for speed! The first TWINSCAN NXE:3800E is now being installed in a chip fab. 🔧

With its new wafer stages, the system will deliver leading edge productivity for printing advanced chips. We're pushing lithography to new limits. 💪 pic.twitter.com/y5hJg5Tdot

— ASML (@ASMLcompany) March 12, 2024

ASML has not published the full details on the capabilities of the machine, but previous roadmaps from the company have indicated that the updated 3800E would offer both improved wafer throughput and increased wafer alignment precision – what ASML refers to as "matched-machine overlay". Based on that roadmap, ASML is expecting to crack 200 wafers per hour with their fifth-generation low-NA EUV scanner, which would mark a significant milestone for the technology, as one of the drawbacks of EUV lithography since the beginning has been its lower throughput rate compared to today's extremely well-researched and tuned deep UV (DUV) machines.

For ASML's logic and memory fab customers – a list these days that is only around half a dozen companies in total – the updated scanner will help these foundries continue to improve and expand their production of leading-edge chips. Even with major fabs in the midst of scaling-up their operations with additional facilities, improving throughput at existing facilities remains an important factor in meeting capacity demands, as well as bringing down production costs (or at least, keeping them in check).

Though as EUV scanners don't come cheap – a typical scanner costs some $180 million and the Twinscan NXE:3800E will likely cost more – it'll take a while to fully amortize these machines. In the meantime, shipping a faster generation of EUV scanners will have significant financial implications for ASML, who is already enjoys the status (and criticism) that comes from being the sole supplier of such a critical tool.

Following the 3800E, ASML has at least one more generation of low-NA EUV scanners in the works, with the development of the Twinscan NXE:4000F. That's expected to be released around 2026.

Source: ASML (via Computerbase)

Marvell this week introduced its new IP technology platform specifically tailored for custom chips for accelerated infrastructure made on TSMC's 2nm-class process technologies (possibly including N2 and N2P). The platform includes technologies essential for developing cloud-optimized accelerators, Ethernet switches, and digital signal processors.

"The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure," said Sandeep Bharathi, chief development officer at Marvell. "Our partnership with TSMC on our 5nm, 3nm and now 2nm platforms has been instrumental in helping Marvell expand the boundaries of what can be achieved in silicon."

The 2nm platform is built on Marvell's extensive IP portfolio, which includes advanced SerDes capable of speeds beyond 200 Gbps, processor subsystems, encryption engines, SoC fabrics, and high-bandwidth physical layer interfaces. These IPs are crucial for developing and producing a range of devices, such as custom compute accelerators and optical interconnect digital signal processors. These are becoming common building blocks for AI clusters, cloud data centers, and other infrastructures supporting machines used for AI and HPC workloads.

While these IPs are vital for a variety of processors, DSPs, and networking gear, developing them from scratch—especially for TSMC's 2nm-class process technologies that rely on gate-all-around Nanosheet transistors—is hard, time-consuming, and sometimes inefficient, both from a die space and economics point of view. This is where Marvell's IP portfolio promises to be very useful.

Marvell does not outright say that its TSMC 2nm-certified platform is silicon-proven, but given the fact that TSMC has been working with IP providers over N2-compatible IPs for quite some time, it is reasonable to expect that at least some of Marvell's popular IPs are.

"We take a modular approach to semiconductor design R&D, focusing first on qualifying foundational analog, mixed-signal IP and advanced packaging that can be used across a broad spectrum of devices," Bharathi said. "This allows us to bring innovations such as process manufacturing advances faster to market."

Meanwhile, Marvell is not part of TSMC's Open Innovation Platform and OIP's IP Alliance, so it is unclear whether the company's N2-compatible IPs will be part of TSMC's TSMC9000 IP program, which greatly simplifies IP choices for chip designers.

"TSMC is pleased to collaborate with Marvell in pioneering a platform for advancing accelerated infrastructure on our 2nm process technology," said Kevin Zhang, senior vice president of business development at TSMC. "We are looking forward to our continued collaboration with Marvell in the development of leading-edge connectivity and compute products utilizing TSMC's best-in-class process and packaging technologies."

Source: Marvell

As Intel prepares to move its fabs into its new Intel Foundry business, it will change the way it reports results in the coming months. To discuss the company's long-term vision and give investors a better understanding of how Intel's business will move forward with Intel Foundry and Intel Products groups, Intel plans to host a webinar on segment reporting on April 2, 2024.

"The webinar will discuss the longer-term vision for the foundry business and the importance of establishing a foundry-like relationship between Intel Foundry, Intel's manufacturing organization, and Intel Products, its product business units, to drive greater transparency and accountability," the description of the event reads.

The company plans to submit an 8-K form, revising its past financial reports to align with a new reporting framework, before the upcoming investor webinar. Starting with Q1 FY2024, Intel will disclose its financial outcomes using this new reporting structure.

One of the things that Intel will touch upon at the webinar is the financial and market performance of the Intel Foundry division. These things may not impress. It is likely that initially, Intel Foundry's business will have high costs, and the majority of orders will come from Intel itself (i.e., a significant but still relatively low market share). Meanwhile, Intel Foundry has to invest in advanced fab tools to prep its fabs for 20A and 18A, which drives its costs up, and this likely means losses.

Yet, it will take some time before Intel Foundry obtains revenue streams from major customers, such as Microsoft or the U.S. military. IF's financial numbers and market share may still not impress immediately, but this is normal at this stage. This is perhaps what Intel will communicate and discuss at its upcoming webinar.

In fact, although Intel fully expects its 18A (1.8nm-class) fabrication process to be ahead of its rivals in terms of power, performance, and area (PPA), the company's chief financial officer reiterated at a conference this week that it does not expect to win the bulk of any large customer's chip orders with this technology.

"We probably will not win anybody's major volume [with] 18A," said David Zisner, CFO of Intel, at the Morgan Stanley Technology, Media, and Telecom Conference (via SeekingAlpha). "We will win some smaller SKUs, and that is all we need, to be honest with you. That will be very significant to us, even though it seems maybe marginal in the marketplace, particularly if we can collect enough of these customers [developing high-performance compute chips]."

Intel's 18A fabrication process builds upon the company's 20A manufacturing technology (a 2nm-class node) that introduces RibbonFET gate-all-around transistors and PowerVia backside power delivery network. In GAA transistors, horizontal channels are fully encased by gates. These channels are built using epitaxial growth and selective removal, enabling adjustments in width for enhanced performance or lower power use. As for the backside power delivery network (BS PDN), the technique moves power lines to the wafer's back, separating them from I/O wiring, which allows for making power vias thicker and reducing their resistance, which helps to both increase transistor performance and lower power consumption.

Both GAA transistors and BS PDN promise to offer significant performance and power efficiency enhancements, which is good for AI, HPC, and smartphone SoCs. Meanwhile, 18A promises a 10% performance per watt improvement over 20A and GAA innovations. Thus, it promises to be quite competitive compared to TSMC's N3B and N3P.

"When it comes to the high-performance compute part of the market, that is really where we are starting to see a lot of our uptake," said Zisner. "The particular aspects of 18A with PowerVia and RibbonFET, combined with our just legacy of experience on high-performance compute, I think, makes us a really compelling partner for customers that are in that space and want to develop products."

Intel's 18A was designed to be a major foundry node, and consequently, its process design kit (PDK) is now available and the production technology is compatible with third-party electronic design automation (EDA) and simulation tools. However, Intel itself does not expect this process to be used for high-volume products of third parties. Even Microsoft is currently only slated to produce one chip on Intel's 18A.

Intel Foundry is a newcomer to the contract chipmaking market. As a result, Intel is planning for a multi-generational effort to break into the market, as the company will need to earn the confidence and business of third-party customers. As this happens, Intel Foundry expects to gain market share and reach profitability.

Sources: Intel, SeekingAlpha

5 nodes in 4 years. This is what Intel CEO Pat Gelsinger promised Intel’s customers, investors, and the world at large back in 2021, when he laid out Intel’s ambitious plan to regain leadership in the foundry space. After losing Intel’s long-held spot as the top fab in the world thanks to compounding delays in the 2010s, the then-new Intel CEO bucked calls from investors to sell off Intel’s fabs, and instead go all-in on fabs like Intel has never done before, to become a top-to-bottom foundry service for the entire world to use.

Now a bit over two years later, and Intel is just starting to see the first fruits from that aggressive roadmap, both in terms of technologies and customers. Products based on Intel’s first EUV-based node, Intel 4, are available in the market today, and its high-volume counterpart, Intel 3, is ready as well. Meanwhile, Intel is putting the final touches on its first Gate-All-Around (GAAFET)/RibbonFET for 2024 and 2025. It’s a heady time for the company, but it’s also a critical one. Intel has reached the point where they need to deliver on those promises – and they need to do so in a very visible way.

To that end, today Intel’s Foundry group – the artist formally known as Intel Foundry Services – is holding its first conference, Direct Connect. And even more than being a showcase for customers and press, this is Intel’s coming-out party for the fab industry as a whole, where Intel’s foundry (and only Intel’s foundry) gets the spotlight, a rarity in the massive business that is Intel.