Following Intel’s painful Q2 earnings call and the announcement of their 2025 cost reduction plan last week, it has become increasingly evident that Intel’s future is in the hands of their foundry group. Between Intel’s IDM 2.0 initiative and their internal chip production plans, all roads lead back to Intel retaking – and retaining – fab process leadership. To win as both a chip designer and a contract chip maker, Intel needs to be able to regain the fab technology lead it once held. In many respects it’s a return to Intel’s classic (and most successful) operating model, but never has it been so risky at it is for the already weakened Intel.
Intel’s do-or-die dash for process leadership means that, for the next 18 months or so, all eyes are on the company’s 20A and 18A process nodes. The final nodes in their ambitious 5 Nodes in 4 Years roadmap, the twinned 20A/18A are the culmination of several new technologies, primarily Intel’s GAAFET implementation (RibbonFET), which is being combined with PowerVia, Intel’s backside power delivery network (BS-PDN) technology. 20A is set to serve as Intel’s early version of the node, and 18A the refined version for long-term use both internally, and as the first major external node for Intel Foundry. To say that everything rides on Intel 18A isn’t quite accurate, but it’s only a slight embellishment.
To that end, we’re going to see Intel deliver a lot of status updates on 18A over the next year as they continue to outline to investors and external customers alike that they have the manufacturing side of their business in order. And today is one of those days, with a fresh update on the state of 18A.
18A Chips Back & Booting
So what’s new with 18A? The biggest news out of Intel this morning is that their first 18A chips are back from the development fab and are successfully booting operating systems. This means the silicon not only works (power-on), but works well enough to complete core tasks. It’s a major step in bringing up a chip, and at this point, Intel wants to make sure to let the whole world know.
Earlier this year the company finished taping out both of its lead 18A chips: Panther Lake for clients, and Clearwater Forest for servers. And it’s both chips that are booting. This is made all the more significant by the fact that Clearwater Forest also relies on Intel’s die-to-die hybrid bonding packaging technology, Foveros Direct 3D, where it will be the lead product for that technology as well. Which for Intel, is a promising sign that not only are their silicon lithography ambitions paying off, but their intention to lead in advanced packaging is on-track as well.
And while Intel doesn’t normally talk about yields this early in the game, it’s interesting to note that in a separate Q&A being published this morning with Intel Foundry’s new boss, Kevin O’Buckley, the head of Foundry Services explicitly comments that Panther Lake is “yielding well”. Similarly, Panther Lake’s DDR memory controller (a complex block mixing logic with a PHY) is already running at its target frequency. Progress is going so well, apparently, that according to O’Buckley, it’s ahead of schedule on its product qualification milestones.
PDK 1.0 Released, First External Customer Tape-Out Expected in H1’25
As for Intel’s contract foundry business, the company is ramping up its efforts there now that the first full process design kit (PDK) is ready for 18A. Intel released their 18A PDK 1.0 last month, giving Intel’s customers (and potential customers) the tools to finally finish designing their chips for production. As is typically the case of a new node, pre-release PDKs were available for companies to get started on their designs, but the 1.0 PDK is typically needed to finish those designs and align them with the formal and finalized process specifications.
For Intel, getting an external PDK out for a leading-edge process node is no small feat, as the company has spent decades operating its fabs for the benefit of its internal product design teams. A useful PDK for external customers – and really, a useful fab environment altogether – not only needs process nodes that stick to their specifications rather than making bespoke adjustments, but it means that Intel needs to document and define all of this in a useful, industry standard fashion. One of the major failings of Intel’s previous efforts to get into the contract foundry business, besides being half-hearted efforts overall, is that they didn’t author PDKs that external companies could easily use. At the end of the day, Intel is looking to woo customers from TSMC and Samsung, and as such Intel needs to provide PDKs that chip designers accustomed to contemporary contract fabs can use.
Those efforts are finally paying off, if slowly. While still not sharing any names, Intel expects their first external customer chip design will tape out in the first half of 2025 (H1’25). And, as Intel hopes, it will be the first of many.
Ultimately, the hard work for Intel foundry is not yet complete, and it will continue from here. With initial 18A development wrapping up, Intel’s needs are no longer just fab R&D, but marketing and customer relations. Which, going back to the start of this article, is why Intel is so keen to release status updates on 18A: it’s part of a broader approach to entice new customers to give Intel a try. Even in the best-case scenario, it will take upwards of a decade to capture a majority of the market for fabbing cutting-edge chips. But Intel has to start that marketing push if they’re going to get there.
In the meantime, if all continues going well for Intel, we should be seeing the first 18A chips released in the latter half of near year.
Solidigm's datacenter SSD lineup includes models targeting different performance, endurance, and cost tradeoffs. Last year, the company had introduced the D5-P5336 QLC drive as a low-cost high-capacity drive for read-heavy workloads, while also preparing the SLC-based D7-P5810 for extremely write-intensive workloads requiring high endurance. The D7-P5520 / D7-P5620 Gen 4 drives with Solidigm's own 144L 3D TLC have been the high-performance offerings for generic workloads over the last couple of years.
Solidigm is announcing the availability of the successor to the D7-P5x20 today - the new D7-PS1010 and D7-PS1030. Both of these NVMe drives use SK hynix's 176L 3D TLC NAND and come with a PCIe 5.0 interface. The third digit in the model number matches the DWPD rating, with the D7-PS1010 targeting mixed workloads with a 1 DWPD rating, and the D7-PS1030 targeting write-intensive use-cases with a 3 DWPD rating.
Compared to the previous generation D7-P5x20, the D7-PS10x0 series brings about the following upgrades:
Move from PCIe 4.0 x4 to PCIe 5.0 x4
Move from 144L floating gate 3D TLC (Solidigm) to 176L charge trap 3D TLC (SK hynix)
25% longer mean-time between failures (MTBF) at 2.5M hours
10x higher uncorrectable bit-error rate (UBER) at 1E-18
1.8x to 2.8x improvement in high queue-depth random access IOPS
2.0x to 2.2x improvement in high queue-depth sequential access throughput
The specifications of the two new SSD families are summarized in the table below.
2.35 M (1.6 TB / 1.92 TB)
3.1 M (3.2 TB / 3.84 TB)
2.8 M (6.4 TB / 7.68 TB)
2.75 M (12.8 TB / 15.36 TB)
Random Write (4 kB)
0.35 M (1.6 TB)
0.716 M (3.2 TB)
0.8 M (6.4 TB / 12.8 TB)
0.15 M (1.92 TB)
0.315 M (3.84 TB)
0.4 M (7.68 TB)
0.38 M (15.36 TB)
Power
Sustained Write
13 W (1.6 TB / 1.92 TB)
18 W (3.2 TB / 3.84 TB)
23 W (6.4 TB / 7.68 TB / 12.8 TB / 15.36 TB)
Sustained Read
17 W (1.6 TB / 1.92 TB)
19 W (3.2 TB / 3.84 TB)
22 W (6.4 TB / 7.68 TB)
23 W (12.8 TB / 15.36 TB)
Peak
18 W (1.6 TB / 1.92 TB)
22 W (3.2 TB / 3.84 TB)
29 W (6.4 TB / 7.68 TB)
30 W (12.8 TB / 15.36 TB)
Idle
5 W
Write Endurance
3 DWPD
1 DWPD
Warranty
5 years
Based on Solidigm's own internal testing, the D7-PS1010 compares very favorably against the Gen 5 datacenter SSDs already in the market from Samsung and Kioxia. However, the recently introduced Micron 9550 series may present a better challenge to Solidigm's claims.
Gen 5 SSDs are well-suited for the storage-intensive tasks in AI workloads. Every new product needs to tie itself to the AI buzzword currently, but we should excuse SSD manufacturers for doing the same - after all training and inference needs to move large amounts of data back and forth between the processing engine and underlying memory. Solidigm expects the D7-PS10x0 to be a good fit as direct-attached storage internal to GPU servers or as all-flash tier supporting a HDD-only object tier in the cloud. For on-premises GPU servers, the flash / HDD tiered storage can be replaced by an all-QLC object tier.
Solidigm claims better energy efficiency compared to the competitors' Gen 5 drives from last year for various AI workload traces. While the data ingest and archival processes require system designers to maximize the storage capacity per watt (the QLC-based Solidigm D5-P5336 is attractive here), the core processing steps require the optimization of performance per watt. The D7-PS10x0 have a natural fit in this segment.
Solidigm / Intel has been serving the datacenter SSD market since its inception. The company is well aware of the quality and reliability requirements in this space. The D7-PS1010 and D7-PS1030 include the usual enhanced PLI (power loss imminent) validation checks for data saved in the process of power loss / restoration. The critical SRAMs in the SSD controller also have ECC protection. UBER testing goes well beyond the suggested JEDEC specifications. The company also claims that its silent data corruption testing and modeling are better than its competitors.
The new D7-PS1010 and D7-PS1030 bring class-leading Gen 5 performance to the datacenter SSD market. They are available for purchase now in both U.2 and E3.S form factors, with capacities ranging from 1.6 TB - 12.8 TB (D7-PS1030) and 1.92 TB - 15.36 TB (D7-PS1010).
Samsung is announcing today that it has begun mass production of 12 GB and 16 GB LPDDR5X modules in the industry's thinnest package. Samsung's shrunken memory packages measure approximately 0.65 mm in thickness, making them 0.06 mm (~9%) thinner than standard LPDDR5X packages. The company expects the new DRAM devices to be used to make for thinner smartphones, or improve their performance by enabling better airflow inside.
According to the company's press release, Samsung achieved this ultra-thin design by employing new packaging methods, such as optimized printed circuit boards (PCBs) and epoxy molding compound (EMC). Additionally, an optimized back-lapping process was used to further reduce the height of the packages. The newly developed DRAM packages are not only thinner by 9% compared to previous models but also offer a 21.2% improvement in heat resistance.
Thinner LPDDR5X packaging help enhance airflow within smartphones, significantly improving thermal management, which means higher performance and longer battery life. Also, better thermal management help to prolong device's lifespan.
"Samsung's LPDDR5X DRAM sets a new standard for high-performance on-device AI solutions, offering not only superior LPDDR performance but also advanced thermal management in an ultra-compact package," said YongCheol Bae, Executive Vice President of Memory Product Planning at Samsung Electronics. "We are committed to continuous innovation through close collaboration with our customers, delivering solutions that meet the future needs of the low-power DRAM market."
While Samsung's thinner LPDDR5X DRAM packages contribute to making smartphones slimmer, they are just one part of the overall design strategy. Other components, such as thinner protective glass, PCBs, and batteries, play considerably more significant roles in reducing device thickness. Meanwhile, the primary benefit of these new memory modules may be in improving airflow inside smartphones.
Samsung is looking to further expand its LPDDR5X product lineups by developing even more compact packages, including 6-layer 24 GB and 8-layer 32 GB modules. Specific details about the thickness of these future memory modules have not yet been disclosed, though making high-capacity DRAMs thinner in general is an important thing.
In an unexpected announcement during their quarterly earnings call this week, Western Digital revealed that it has begun sampling an upcoming 32TB hard drive. The nearline HDD is aimed at hyperscalers, and relies on a combination of Westen Digital's EAMR technology, as well as shingled magnetic recording (SMR) technology to hit their highest capacity figures to date.
Western Digital's 32TB HDD uses all of the company's most advanced technologies. Besides energy-assisted magnetic recording (EAMR/ePMR 2 to be more precise) technology, WD is also leveraging triple-stage actuators for better positioning of heads and two-dimensional (TDMR) read heads, OptiNAND for extra performance and reliability, distributed sector (DSEC) technology and a proprietary error correcting code (ECC) technology. And, most importantly, UltraSMR technology to provide additional capacity.
"We are shipping samples of our 32TB UltraSMR/ePMR nearline hard drives to select customers," said David Goeckeler, chief executive of Western Digital, at the earnings call. "These drives feature advanced triple-stage actuators and OptiNAND technology which are designed for seamless qualification, integration and deployment in hyperscale cloud and enterprise data centers while maintaining exceptional reliability."
As with the comapny's other UltraSMR drives, the 32TB nearline drive is aimed at WD's enterprise customers, whose infrastructure can handle the additional management requirements that SMR imposes. As SMR in enterprise drives is not transparent, it's up to the host to manage many of the complexities that come with a hard drive that isn't suited for random writes. Though at least in WD's case, the upshot is that UltraSMR also offers a more significant density increase than other SMR implementations, using a larger number of SMR bands to increase HDD capacity by up to 20%.
Working backwards, that 20% capacity increase also means that WD's new drive is starting from 2.56TB CMR platters. And while 2.56TB makes for a very decent areal density, this would mean that WD is still behind rival Seagate in terms of areal density overall, as Seagate has 3TB CMR platters in its latest HAMR-based Exos drives.
The trend towards miniaturization of desktop systems was kickstarted by the Intel NUCs in the early 2010s. The increasing popularity of compact PCs also led to the introduction of a variety of slightly larger form-factors. Custom boards falling in size between the NUC's 4" x 4" ultra-compact form-factor (UCFF) and industrial-applications oriented 3.5" SBC have also gained traction. The ECS LIVA Z5 PLUS is one such system, designed and marketed towards business and industrial use-cases.
Intel's Raptor Lake series of products was introduced in early 2023. It came in both P and U versions for notebooks and ultraportables, in addition to the usual H(X) ones for high-performance gaming notebooks. Most mini-PCs and NUCs opted for the P varieties in their systems. The ECS LIVA Z5 PLUS represents a different take, with a U series processor operating with a slight increase in the configurable TDP (cTDP) over Intel's suggested 15W operating point. Read on for a comprehensive look at the performance and features of the ECS LIVA Z5 PLUS, including some comments on the benefits enabled by the slightly larger form-factor.
Update 08/06: Intel published an additional note on Monday, confirming which SKUs are covered by the program. The full list of SKUs has been added to the article below, but it's essentially the 13600K/14600K and above – all of Intel's high-TDP desktop parts using the Raptor Lake B0 die.
Capping off an extensive (and expensive) week for Intel, the company has also announced that they are taking additional steps to address the ongoing chip stability issues with desktop Raptor Lake chips – the 13th and 14th Generation desktop Core processors. In order to keep owners whole, Intel will be extending the warranty on retail boxed Raptor Lake chips by two years, bringing the cumulative warranty for the chips to five years altogether.
This latest announcement comes as Intel is still in the process of preparing their major Raptor Lake microcode update, which is designed to mitigate the issue (or rather, further damage) by fixing the elevated voltage bug in their existing microcode that has led to the issue in the first place. That microcode update remains scheduled for mid-August, roughly a couple of weeks from now.
But until then – and depending on how quickly the update is distributed, even afterwards – there is still the matter of what to do with Raptor Lake desktop chips that are already too far gone and are consequently unstable. Intel’s retail boxed Raptor Lake chips ship with a 3 year warranty, which given the October 2022 launch date, would have the oldest of these chips covered until October of 2025 – a bit over a year from now. And while the in-development fix should mean that this is plenty of time to catch and replace any damaged chips, Intel has opted to take things one step further by extending the chips’ warranty to five years.
Overall, this is much-needed bit of damage control by Intel to restore some faith in their existing Raptor Lake desktop processor lineup. Even with the planned microcode fix, it remains unclear at best about what the long-term repercussions of the voltage bug is, and what it means for the lifespan of still-stable chips that receive the fixed microcode. In the best-case scenario, an extended warranty gives Raptor Lake owners a bit more peace of mind, and in a worst-case scenario, they’re now covered for a couple of years longer if the chip degradation issues persist.
One important thing to note, however, is that the extended warranty will only apply to boxed processors, i.e. Intel’s official retail chips. Intel’s loose chips that are sold by the tray to OEMs and certain distributors – commonly referred to as “tray” processors – are not covered by the extended warranty. While Raptor Lake tray processors do technically come with a three-year warranty of their own, Intel does not provide direct, end-user warranty service for these chips. Instead, those warranties are serviced by the OEM or distributor that sold the chip.
With the bulk of Intel’s chips going to OEMs and other professional system builders, Intel will undoubtedly need to settle things with those groups, as well. But with OEM dealings typically remaining behind closed doors, it’s unlikely we’ll hear about just what is agreed there. Regardless, whatever Intel does (or doesn’t do) to assuage OEMs and distributors, those groups will remain responsible for handling warranty claims for tray chips.
Finally, it should be noted that while today’s announcement outlines the two-year warranty extension, it doesn’t deliver the full details on the program. Intel expects to release more details on the extended warranty program “in the coming days.”
Intel’s full statement is below:
Intel is committed to making sure all customers who have or are currently experiencing instability symptoms on their 13th and/or 14th Gen desktop processors are supported in the exchange process. We stand behind our products, and in the coming days we will be sharing more details on two-year extended warranty support for our boxed Intel Core 13th and 14th Gen desktop processors.
In the meantime, if you are currently or previously experienced instability symptoms on your Intel Core 13th/14th Gen desktop system:
For users who purchased systems from OEM/System Integrators – please reach out to your system manufacturer’s support team for further assistance.
For users who purchased a boxed CPU – please reach out to Intel Customer Support for further assistance.
At the same time, we apologize for the delay in communications as this has been a challenging issue to unravel and definitively root cause.
-Intel Community Post
On Monday, Intel published an additional post outlining the specific SKUs covered by the extended warranty program. As the voltage/instability issues are thought to only affect high-TDP chips using Intel's Raptor Lake B0 die, which was used for both the 13th Gen and 14th Gen Core processors, the extended warranty program is also being setup to cover those processors specifically. In other words, only chips that are capable of being affected by the issue are receiving the extended warranty.
The rest of Intel's messaging is essentially unchanged from last week, telling customers of boxed processors to contact Intel directly, while tray processor owners need to contact their retailer/OEM.
Following Intel’s earlier announcement regarding two (2) year warranty extension – from date of purchase, up to a maximum of five (5) years - on Intel Core 13th/14th desktop processors, please see below for additional details on the program. Intel Core 13th/14th Gen Desktop Boxed/Tray CPUs
The following processors are covered by the warranty extension:
Processor Number
13th Generation Intel Core
14th Generation Intel Core
i9-13900KS
i9-14900KS
i9-13900K
i9-14900K
i9-13900KF
i9-14900KF
i9-13900F
i9-14900F
i9-13900
i9-14900
i7-13700K
i7-14700K
i7-13700KF
i7-14700KF
i7-13790F
i7-14790F
i7-13700F
i7-14700F
i7-13700
i7-14700
i5-13600K
i5-14600K
i5-13600KF
i5-14600KF
Warranty extension applies to new & previously purchased processors, if they are one of the Intel Core 13th/14th Gen SKUs listed above. This warranty coverage applies to all customers globally.
For users who are or have previously experienced instability symptoms on their Intel Core 13th/14th Gen Desktop processors and need to initiate the exchange process:
Boxed Processors – please contact Intel Customer Support for further assistance.
Tray Processors – please contact your place of purchase for further assistance.
OEM/System Integrator Intel Core 13th/14th Gen-powered desktop system – please contact your system manufacturer for further assistance.
If customers have experienced these instability symptoms on their 13th and/or 14th Gen desktop processors but were unsuccessful in prior RMAs we ask that they reach out to Intel Customer Support for further assistance and remediation.
We appreciate your patience with this process and will continue to share updates relating to the Intel Core 13th/14th Gen desktop processor instability issue.
-Intel Community Post (08/05/2024)
Additional Details on Via Oxidation Issue
Separately, Intel’s community team also posted a brief update on the via oxidation issue that, although distinct from the current Raptor Lake instability issues, came into question at roughly the same time. Intel has previously stated that that issue is unconnected to the ongoing stability issues, and was fixed back in 2023. And this latest update offers a few more details on just what that manufacturing issue entailed.
The Via Oxidation issue currently reported in the press is a minor one that was addressed with manufacturing improvements and screens in early 2023.
The issue was identified in late 2022, and with the manufacturing improvements and additional screens implemented Intel was able to confirm full removal of impacted processors in our supply chain by early 2024. However, on-shelf inventory may have persisted into early 2024 as a result.
Minor manufacturing issues are an inescapable fact with all silicon products. Intel continuously works with customers to troubleshoot and remediate product failure reports and provides public communications on product issues when the customer risk exceeds Intel quality control thresholds.
-Intel Community Post
Update 08/02: Patrick Moorhead has published a further tweet, clarifying that "Pat [Gelsinger] didn’t tell me l that there were yield issues. This was *my* interpretation." The text of the article has been updated accordingly to reflect this tweet, as well as Intel statements about accelerating their Ireland Fab 34 ramp-up.
Alongside Intel’s weak Q2 2024 earnings report and the announcement of $10 billion in spending cuts and layoffs for 2025, the company is also disclosing some new information about their chip deliveries over the first half of the year. A brief report, posted on X by analyst Patrick Moorhead and citing a conversation with Intel CEO Pat Gelsinger, revealed that Intel encountered a major production bottleneck on Meteor Lake earlier this year. The issue was significant enough to drive intel to take the extraordinary and costly step of accelerating their Ireland fab ramp-up in order to improve chip capacity.
It was a very rough Q2 for $INTC. And that guide... Thanks, @Pgelsinger, for the time to discuss.
It appears that there were yield/throughput issues on Meteor Lake, negatively impacting gross margins. When you have to get the product to your customers, and you have wafers to… pic.twitter.com/pHU66xvFe7
It appears that there were yield/throughput issues on Meteor Lake, negatively impacting gross margins. When you have to get the product to your customers, and you have wafers to burn, you run it hot. I heard from OEMs that they needed more MTL, but it wasn't bone dry. You have to run hot lots in that case, or else your customers will be impacted. I didn't have this one on my dance card.
-Patrick Moorhead
In a separate tweet posted several hours later, Moorhead then clarified that the yield issues mentioned in his first tweet were his interpretation of the matter, rather than something Pat Gelsinger had told him directly.
For the record, Pat didn’t tell me l that there were yield issues. This was *my* interpretation. But when your COGS are cited for a specific product are rising in a big, big way, with MTL, you *have* to surmise either yield or back end throughout issues that can be very expensive.
-Patrick Moorhead
Decoding Moorhead’s dense tweets, fundamentally, Moorhead is questioning why Intel's Cost of Goods Sold (COGS) – how much the company's chips cost to produce – were on the rise with the launch of Meteor Lake. The analyst surmised that yields and/or some other unexpected production bottleneck must be the case, as these are the typical issues that drive up chip COGS on a short-term basis like Intel has been experiencing.
And, judging from Intel's earnings call that took place after the initial tweet, Moorhead was right to an extent. Referencing the increased COGS, Intel CFO David Zinsner noted that Intel opted to ramp up its high-volume production in Ireland faster than initially planned. This increased Intel's capacity for Intel 4 (and Intel 3) capacity, but doing so also increased their costs, as wafers out of Ireland cost more in the near term.
The largest impact was caused by an accelerated ramp of our AI PC product. In addition to exceeding expectations on Q2 Core Ultra shipments, we made the decision to accelerate transition of Intel 4 and 3 wafers from our development fab in Oregon to our high volume facility in Ireland, where wafer costs are higher in the near term.
-Intel CFO David Zinsner (Intel Q2'24 Earnings Call)
Between Moorhead's report that OEMs have been receiving fewer Meteor Lake chips than they could use, and Intel's announcement that they accelerated the Ireland fab ramp-up, this is the first significant disclosure that Meteor Lake chips were, at least at some point, in unexpectedly short supply. Which in turn required Intel to take unexpected and extraordinary steps in order to improve chip production, at the cost of lower short-term profit margins and higher COGS.
The first of Intel's high-volume manufacturing (HVM) fabs to be equipped for the Intel 4 and Intel 3 processes, Fab 34 in Ireland is a critical element to Intel's cutting-edge product plans over the next couple years. Intel was not initially planning on relying so much on Fab 34 this soon – instead using their Oregon development fabs to do more of their Intel 4 & Intel 3 fabrication – but the company opted to ramp up at a faster pace. The benefit to Intel is that they get more fab capacity sooner, but it means they're incurring around $1 billion in costs now of what would have otherwise been spread out over further quarters during a more gradual ramp-up.
The net result was that, while Intel took a margin hit, it also allowed them to supply more Meteor Lake chips than they otherwise would have, even beating their own previous projections for Q2 shipments. Overall, Intel reported in their Q2 earnings that they’ve shipped 15 million “AI PC” chips since Meteor Lake’s launch, though the company doesn't break down how many of those were in Q2 versus Q1 and Q4'23. Still, according to Moorhead, this was fewer chips than OEMs would have liked to have, and they would have taken more chips if they were available.
COGS and Ireland ramp-ups aside, Moorhead also posits that some of Intel's capacity boost came from running “hot lots” of Meteor Lake – high priority wafer batches that get moved to the front of the line in order to be processed as soon as possible (or as reasonably close as is practical). Hot lots are typically used to get highly-demanded chips produced quickly, getting them through a fab sooner than the normal process would take. As a business tool, hot lots are a fact of life of chip production, but they’re undesirable because in most cases they cause disruptions to other wafers that are waiting their turn to be processed.
If true, running hot lots of Meteor Lake would be a significant development given the potential disruptions. At the same time, however, the situation with Meteor Lake is somewhat particular, as the Intel 4 process used for Meteor Lake’s compute tile (the only active tile made at Intel) is not offered to external foundry customers, or even used by other Intel CPUs (Xeon 6s all use Intel 3). So hot lots of Meteor Lake would have few other wafers to even jump ahead of for EUV tooling (Intel would certainly not put them ahead of high-margin Xeon products), while it's unclear how this would cascade down to any tools shared with Intel 7.
Intel, for their part, did not comment on Meteor Lake chip yields or hot lots in their earnings call.
In any case, Intel at this point is looking to turn around their troubled fortunes in the second half of this year. The company’s next-gen client SoC for mobile, Lunar Lake, is set to launch on September 3rd. And notably, both of its active tiles are being built by TSMC. So Lunar Lake would be spared from any Intel logic fab bottlenecks, though it still has to go through Intel’s facilities for assembly using their Foveros technology. And there remains the thorny issue of higher production costs altogether, since Intel is paying for what's effectively the fully outsourced production of a Core CPU.
Amidst the backdrop of a weak quarterly earnings report that saw Intel lose money for the second quarter in a row, Intel today has announced that the company will be cutting costs by $10 billion in 2025 in an effort to bring Intel back to profitability. The cuts will touch almost every corner of the company in some fashion, with Intel planning to cut spending on R&D, marketing, administration, and capital expenditures. The most significant of these savings will come from a planned 15% reduction in force, which will see Intel lay off 15,000 employees over the next several months – thought to be one of Intel’s biggest layoffs ever.
In an email to Intel’s staff, which was simultaneously published to Intel’s website, company CEO Pat Gelsinger made the financial stakes clear: Intel is spending an unsustainable amount of money for their current revenues. Citing the company’s current costs, Gelsinger wrote that “our costs are too high, our margins are too low,“ and that “our annual revenue in 2020 was about $24 billion higher than it was last year, yet our current workforce is actually 10% larger now than it was then.” Consequently, Intel will be enacting a series of painful cuts to bring the company back to profitability.
Intel is not publicly disclosing precisely where those cuts will come from, but in the company’s quarterly earnings release, the company noted that it was targeting operating expenses, capital expenditures, and costs of sales alike.
For operating expenses, Intel will be cutting “non-GAAP R&D and marketing, general and administrative” spending, with a goal to trim that from $20 billion in 2024 to $17.5 billion in 2025. Meanwhile gross capital expenditures, a significant expense for Intel in recent years as the company has built up its fab network, are projected to drop from $25 billion to $27 billion for 2024, to somewhere between $20 billion and $23 billion in 2025. Compared to Intel’s previous plans for capital expenditures, this would reduce those costs by around 20%. And finally, the company is expecting to save $1 billion on the cost of sales in 2025.
Intel 2025 Spending Cuts
2024 Projected Spending
2025 Projected Spending
Projected Reduction
Operating Expenses
(R&D, Marketing, General, & Admin)
$20B
$17.5B
$2.5B
Capital Expenditures (Gross)
$25B - $27B
$20B - $23B
$2B - $7B
Cost of Sales
N/A
$1B Savings
$1B
Separately, in Intel’s email to its employees, Gelsinger outlined that these cuts will also require simplifying Intel’s product portfolio, as well as the company itself. The six key priorities for Intel will include cutting underperforming product lines, and cutting back Intel’s investment in new products to “fewer, more impactful projects”. Meanwhile on the administrative side of efforts, Intel is looking to eliminate redundancies and overlap there, as well as stopping non-essential work.
Reducing Operational Costs: We will drive companywide operational and cost efficiencies, including the cost savings and head count reductions mentioned above.
Simplifying Our Portfolio: We will complete actions this month to simplify our businesses. Each business unit is conducting a portfolio review and identifying underperforming products. We are also integrating key software assets into our business units so we accelerate our shift to systems-based solutions. And we will narrow our incubation focus on fewer, more impactful projects.
Eliminating Complexity: We will reduce layers, eliminate overlapping areas of responsibility, stop non-essential work, and foster a culture of greater ownership and accountability. For example, we will consolidate Customer Success into the Sales, Marketing and Communications Group to streamline our go-to-market motions.
Reducing Capital and Other Costs: With the completion of our historic five-nodes-in-four-years roadmap clearly in sight, we will review all active projects and equipment so we begin to shift our focus toward capital efficiency and more normalized spending levels. This will reduce our 2024 capital expenditures by more than 20%, and we plan to reduce our non-variable cost of goods sold by roughly $1 billion in 2025.
Suspending Our Dividend: We will suspend our stock dividend beginning next quarter to prioritize investments in the business and drive more sustained profitability.
Maintaining Growth Investments: Our IDM2.0 strategy is unchanged. Having fought hard to reestablish our innovation engine, we will maintain the key investments in our process technology and core product leadership.
The bulk of these cuts, in turn, will eventually come down to layoffs. As previously noted, Intel is planning to cut about 15% of its workforce. Just how many layoffs this will entail remains to be seen; Gelsinger’s letter puts it at roughly 15,000 employees, while Intel’s most recent published headcount would put this figure at closer to 17,000 employees.
Whatever the number, Intel is expecting to have most of the reductions completed by the end of this year. The company will be using a combination of early retirement packages and buy-outs, or what the company terms as “an application program for voluntary departures.”
Intel’s investors will be taking a hit, as well. The company’s generous quarterly dividend, a long-time staple of the chipmarker and one of the key tools to entice long-term investors, will be suspended starting in Q4 of 2024. With Intel losing money over multiple quarters, Intel cannot afford (or at least, cannot justify) paying out cash in the forms of dividends when that money could be getting invested in the company itself. Though as the long-term health of the company is still reliant on offering dividends, Intel says that the suspension will be temporary, as the company reiterated its “long-term commitment to a competitive dividend as cash flows improve to sustainably higher levels.” For Q2 2024, Intel paid out $0.125/share in dividends, or a total of roughly $0.5B.
Ultimately, the message coming from Intel today is that it is continuing (if not accelerating) its plans to slim down the company; to focus on a few areas of core competencies that suit the company’s abilities and its financial goals. Intel is throwing everything behind its IDM 2.0 initiative to regain process leadership and serve as a world-class contract foundry, and even with Intel’s planned spending cuts for 2025, that initiative will continue to move forward as planned.
On that note, cheering up investors in what’s otherwise a brutal report from the company, Intel revealed that they’ve achieved another set of key milestones with their in-development 18A process. The company released the 1.0 process design kit (PDK) to customers last month, and Intel has successfully powered-on their first Panther Lake and Clearwater Forest chips. 18A remains on track to be “manufacturing-ready” by the end of this year, with Intel looking to start wafer production in the first half of 2025. 18A remains a make-or-break technology for Intel Foundry, and the company as a whole, as this is the node that Intel expects to return them to process leadership – and from which they can improve upon to continue that leadership.
Although AMD delayed launch of its Ryzen 9000-series processors based on the Zen 5 microarchitecture from July 31, to early and mid-August, the company's partner (and major US retailer) Best Buy briefly began listing the new CPUs today, revealing a very plausible set of launch prices. As per the retailer's product catalog, the most affordable unlocked Zen 5-based processor will cost $279, whereas the highest-performing Zen 5-powered CPU will cost $599 at launch.
AMD will start its Ryzen 9000 series rollout from relatively inexpensive six-core Ryzen 5 9600X and eight-core Ryzen 7 9700X on August 8. Per the Best Buy listing, the Ryzen 5 9600X will cost $279, whereas the Ryzen 7 9700X will carry a recommended price tag of $359. Meanwhile, The more advanced 12-core Ryzen 9 9900X and 16-core Ryzen 9 9950X will hit the market on August 15 at MSRPs of $449 and $599, respectively, based on the Best Buy listing.
AMD Ryzen 9000 Series Processors
Zen 5 Microarchitecture (Granite Ridge)
AnandTech
Cores /
Threads
Base
Freq
Turbo
Freq
L2
Cache
L3
Cache
TDP
MSRP
Ryzen 9 9950X
16C / 32T
4.3GHz
5.7GHz
16 MB
64 MB
170 W
$599
Ryzen 9 9900X
12C / 24T
4.4GHz
5.6GHz
12 MB
64 MB
120 W
$449
Ryzen 7 9700X
8C / 16T
3.8GHz
5.5GHz
8 MB
32 MB
65 W
$359
Ryzen 5 9600X
6C / 12T
3.9GHz
5.4GHz
6 MB
32 MB
65 W
$279
It is noteworthy that when compared to the launch prices of the Zen 4-based Ryzen 7000 processors, the new Zen 5-powered Ryzen 9000 CPUs come in cheaper. The range topping Ryzen 9 5950X started at $799 in 2020, while the Ryzen 9 7950X had a recommended $699 price tag in 2022. By contrast, the top-end Ryzen 9 9950X is listed at $599. Both Ryzen 7 5600X and Ryzen 7 7600X cost $299 at launch, while the upcoming Ryzen 5 9600X will apparently be priced at $279 at launch.
As always with accidental retailer listings, it should be emphasized that AMD has not yet announced official pricing for their Ryzen 9000 CPUs. Given Best Buy's status as one of the largest US electronics retailers, these prices carry a very high probability of being accurate; but none the less, they should be taken with a grain of salt – if only because last-minute price changes are not unheard of with new CPU launches.
Micron on Tuesday announced that the company has begun shipping its 9th Generation (G9) 276 layer TLC NAND. The next generation of NAND from the prolific memory maker, Micron's latest NAND is designed to further push the envelope on TLC NAND performance, offering significant density and performance improvements over its existing NAND technology.
Micron's G9 TLC NAND memory features 276 active layers, which is up from 232-layers in case of Micron's previous generation TLC NAND. At this point the company is being light on technical details in their official material. However in a brief interview with Blocks & Files, the company confirmed that their 276L NAND still uses a six plane architecture, which was first introduced with the 232L generation. At this point we're assuming Micron is also string-stacking two decks of NAND together, as they have been for the past couple of generations, which means we're looking at 138 layer decks.
Micron TLC NAND Flash Memory
276L
232L
(B58R)
176L
(B47R)
Layers
276
232
176
Decks
2 (x138)?
2 (x116)
2 (x88)
Die Capacity
1 Tbit
1 Tbit
512 Gbit
Die Size (mm2)
~48.9mm2
~70.1mm2
~49.8mm2
Density (Gbit/mm2)
~21
14.6
10.3
I/O Speed
3.6 GT/s
(ONFi 5.1)
2.4 GT/s
(ONFi 5.0)
1.6 GT/s
(ONFI 4.2)
Planes
6
6
4
CuA / PuC
Yes
Yes
Yes
On the density front, Micron told Blocks & Files that they have improved their NAND density by 44% over their 232L generation. Which, given what we know about that generation, would put the density at around 21 Gbit/mm2. Or for a 1Tbit die of TLC NAND, that works out to a die size of roughly 48.9mm2, comparable to the die size of a 512Gbit TLC die from Micron's older 176L NAND.
Besides improving density, the other big push with Micron's newest generation of NAND was further improving its throughput. While the company's 232L NAND was built against the ONFi 5.0 specification, which topped out at transfer rates of 2400 MT/sec, their new 276L NAND can hit 3600 MT/sec, which is consistent with the ONFi 5.1 spec.
Meanwhile, the eagle-eyed will likely also pick up on Micron's ninth-generation/G9 branding, which is new to the company. Micron's has not previously used this kind of generational branding for their NAND, which up until now has simply been identified by its layer count (and before the 3D era, its feature size). Internally, this is believed to be Micron's 7th generation 3D NAND architecture. However, taking a page from the logic fab industry, Micron seems to be branding it as ninth-generation in order to keep generational parity with its competitors, who are preparing their own 8th/9th generation NAND (and thus cliam that they are the first NAND maker to ship 9th gen NAND).
And while this NAND will eventually end up in all sorts of devices – including, no doubt, high-end PCIe Gen5 drives thanks to its high transfer rates – Micron's launch vehicle for the NAND is their own Micron 2650 client SSD. The 2650 is a relatively straightforward PCIe Gen4 x4 SSD, using an unnamed, DRAMless controller alongside Micron's new NAND. The company is offering it in 3 form factors – M.2 2280, 2242, and 2230 – with a modest set of capacities ranging from 256GB to 1TB.
Micron's 2650 NVMe SSDs offer sequential read performance of up to 7000 MB/s as well as sequential write performance of up to 6000 MB/s. As for random performance, we are talking about up to a million read and write IOPS, depending on the configuration.
The performance of the drives scales pretty significantly with capacity, underscoring how much parallelism is needed to keep up with the PCIe Gen4 controller. The rated capacity of the drives scales similarly, with the smallest drive rated for 200TBW (800 drive writes), while the largest drive is rated for 600 TBW (600 drive writes).
“The shipment of Micron G9 NAND is a testament to Micron’s prowess in process technology and design innovations,” said Scott DeBoer, executive vice president of Technology and Products at Micron. “Micron G9 NAND is up to 73% denser than competitive technologies in the market today, allowing for more compact and efficient storage solutions that benefit both consumers and businesses.”
Micron's G9 276-layer TLC NAND memory is also in qualification with customers in component form, so expect the company's partners to adopt it for their high-end SSDs in the coming quarters. In addition, Micron plans Crucial-branded SSDs based on its G9 NAND memory..
Continuing our ongoing look at the latest-generation ATX 3.1 power supplies, today we are examining Cooler Master's V Platinum 1600 V2, a recent addition to the company's expansive PSU lineup.
The V Platinum 1600 V2 is designed to cater to top-end gaming and workstation PCs while offering maximum compatibility with modern ATX directives. And while it boasts a massive 1600 Watt output and a long list of features, the V is a workhorse of a power supply rather than a flagship; Cooler Master is aiming the PSU at budget-conscious users who can't justify spending top dollar, but whom none the less need a powerful and relatively efficient (80PLUS Platinum) power supply.
So often we see PSU vendors go for broke on their high-wattage units, since there's a lot of overlap there with the premium market, so it will be interesting to see what Cooler Master can do with a slightly more modest bill of materials.
Intel’s next-generation Core Ultra laptop chips finally have a launch date: September 3rd.
Codenamed Lunar Lake, Intel has been touting the chips for nearly a year now. Most recently, Intel offered the press a deep dive briefing on the chips and their underlying architectures at Computex back in June, along with a public preview during the company’s Computex keynote. At the time Intel was preparing for Q3’2024 launch, and that window has finally been narrowed down to a single date – September 3rd – when Intel will be hosting their Lunar Lake launch event ahead of IFA.
Intel’s second stab at a high volume chiplet-based processor for laptop users, Lunar Lake is aimed particularly at ultrabooks and other low-power mobile devices, with Intel looking to wrestle back the title of the most efficient PC laptop SoC. Lunar Lake is significant in this respect as Intel has never previously developed a whole chip architecture specifically for low power mobile devices before – it’s always been a scaled-down version of a wider-range architecture, such as the current Meteor Lake (Core Ultra 100 series). Consequently, Intel has been touting that they’ve made some serious efficiency advancements with their highly targeted chip, which they believe will vault them over the competition.
All told, Lunar Lake is slated to bring a significant series of updates to Intel’s chip architectures and chip design strategies. Of particular interest is the switch to on-package LPDDR5X memory, which is a first for a high-volume Core chip. As well, Lunar Lake incorporates updated versions of virtually every one of Intel’s architecture, from the CPU P and E cores – Lion Cove and Skymont respectively – to the Xe2 GPU and 4th generation NPU (aptly named NPU 4). And, in a scandalous twist, both of the chiplets/tiles on the CPU are being made by TSMC. Intel isn’t providing any of the active silicon for the chip – though they are providing the Foveros packaging needed to put it together.
Intel CPU Architecture Generations
Alder/Raptor Lake
Meteor
Lake
Lunar
Lake
Arrow
Lake
Panther
Lake
P-Core Architecture
Golden Cove/
Raptor Cove
Redwood Cove
Lion Cove
Lion Cove
Cougar Cove?
E-Core Architecture
Gracemont
Crestmont
Skymont
Crestmont?
Darkmont?
GPU Architecture
Xe-LP
Xe-LPG
Xe2
Xe2?
?
NPU Architecture
N/A
NPU 3720
NPU 4
?
?
Active Tiles
1 (Monolithic)
4
2
4?
?
Manufacturing Processes
Intel 7
Intel 4 + TSMC N6 + TSMC N5
TSMC N3B + TSMC N6
Intel 20A + More
Intel 18A
Segment
Mobile + Desktop
Mobile
LP Mobile
HP Mobile + Desktop
Mobile?
Release Date (OEM)
Q4'2021
Q4'2023
Q3'2024
Q4'2024
2025
Suffice it to say, no matter what happens, Lunar Lake and the Core Ultra 200 series should prove to be an interesting launch.
It’s worth noting, however, that while Intel’s announcement of their livestreamed event is being labeled a “launch event” by the company, the brief reveal doesn’t make any claims about on-the-shelves availability. September 3rd is a Tuesday (and the day after a US holiday), which isn’t a typical launch date for new laptops (for reference, the lightly stocked Meteor Lake launch was a Thursday). So Intel’s launch event may prove to be more of a soft launch for Lunar Lake; we’ll have to see how things pan out in the coming weeks.
Le premier schéma directeur du matériel roulant ferroviaire a été adopté à l'été 2009. Il parvient à son terme, principalement marqué par les commandes de Francilien et de Régio2N, puis l'arrivée - encore timide - des RERng. La production du nouveau matériel...
Il s’est écoulé 15 ans depuis l’adoption en 2009 du premier schéma directeur du matériel roulant ferroviaire d’Ile-de-France. Depuis, le parc a nettement rajeuni, même si les MI79 constituent aujourd’hui les vétérans franciliens.
Le schéma laissait encore en suspens certaines décisions, car le temps était encore à la réflexion compte tenu de la durée de vie résiduelle de certaines séries, notamment les Z2N. Qu’en est-il aujourd’hui ? Quels nouveaux horizons ? Quels sont les points potentiellement en débat ?
Les projets en cours
L’arrivée du RERng série 58000 libèrera les MI2N du RER E qui seront réformées. Sur le RER D, la série 58500 devait initialement libérer les Z2N série 20500 pour qu’elles remplacent les Z2N séries 5600 et 8800 du RER C. Comme on va le voir par la suite, un autre scénario est à l’étude.
Succéder aux Z2N série 8800 sur cette liaison n’était pas évident car il est impossible de cocher toutes les cases. La contrainte de longueur des quais est assez forte, et la dualité des hauteurs (92 cm sur la partie La Défense – Chaville et 55 cm entre Versailles et La Verrière) ne permet pas de rendre complètement accessible la desserte.
Ile-de-France Mobilités a donc décidé de redistribuer le parc de Z50000, ce qui n’est pas sans poser quelques questions : 11 rames longues viendront du réseau Est et 11 rames courtes du réseau Saint-Lazare. Pourtant, à l’est, il faudra pourvoir aux besoins d’une future électrification de Trilport – La Ferté-Milon nécessitant des Z50000. L’hypothèse de RERng série Z58000 en appoint sur les missions Paris – Meaux et sur les Paris – Château-Thierry aurait l’avantage de rationaliser le parc en évitant une série dédiée pour cette dernière.
Mais récupérer 11 rames courtes sur l’exploitation des lignes J et L, c’est quand même beaucoup…
RER C : décision imminente ?
C’est un morceau de choix. Le RER C fait partie de ces casse-têtes franciliens, compte tenu des multiples contraintes d’architecture et de prestations à assurer.
L’option qui semble en cours est d’aller vite, donc d’utiliser des solutions disponibles. Il n’y en a qu’une : le Régio2N, et plus précisément la version « bis », qui avait été envisagée justement dans la perspective d’équipement du RER C, à condition d’adopter le principe de quais bas sur l’ensemble de la ligne. A la différence des autres Régio2N, cette version longue de 103 m est donc équivalente aux Z2N série 20500 et, sous courant continu, elle lève 2 pantographes, ce qui constitue un défaut important des rames circulant actuellement sur les lignes N et R qui n’en lèvent qu’un seul (avec de forts appels d’intensité à la clé).
Dans un premier temps, pourraient n’être équipées que les missions de Dourdan et d’Etampes, ce qui signifie qu’une nouvelle réorganisation de la desserte devra être préalablement décidée pour séparer clairement les missions « grande couronne » du système RER. Ce premier besoin nécessiterait une cinquantaine de rames. Pour l’équipement complet de la ligne actuelle, il en faudrait une bonne centaine de plus. De quoi susciter un peu d’appétit du côté de Crespin…
Préalable tout de même : harmoniser la hauteur des quais sur cette ligne tentaculaire, et en priorité de la gare Bibliothèque François Mitterrand.
Question subsidiaire : que deviendraient les Z20500 dans cette perspective, sachant que la réforme des dernières rames, série 20900, ne devrait en principe intervenir qu’entre 2040 et 2045 ? Ce serait quand même dommage…
Mises en service à partir de novembre 2009, les Nouvelles Automotrices Transilien ont bien vieilli, mais il faudra assurer des opérations de maintenance patrimoniale qui seront l’occasion de rénover les aménagements intérieurs et de procéder à des améliorations sur la vidéosurveillance et l’information voyageurs. Ile-de-France Mobilités a acté le financement de l’opération de 143 rames longues. Cependant, le coût annoncé (1,16 milliards € aux conditions économiques de janvier 2024) est élevé : 8,1 millions €, c’est approximativement le coût d’une rame à la signature du marché en 2006.
Pour autant, hormis l’équipement de la ligne U déjà évoqué, et leur utilisation vers La Ferté-Milon après électrification, il ne devrait pas y avoir d’autres évolutions dans l’affectation de cette série de 360 unités.
Ligne V : un fantôme temporaire ou définitif ?
Depuis la mise en service du T12, la ligne C a été – un peu – simplifiée en supprimant la mission circulaire. Officiellement, une ligne V a été créée entre Versailles Chantiers et Massy-Palaiseau, rendant autonome le tronçon non repris par le tram-train. Cependant, cette ligne V a bien du mal à marquer son terrain, la signalétique restant fidèle à l’ancienne appellation.
Initialement, cette solution ne devait être que transitoire en attendant le prolongement à Versailles du T12. Celui-ci a pris du plomb dans l’aile : en cause, les passages à niveau, en particulier celui de Jouy-en-Josas, du fait du renforcement de desserte envisagé, avec une fréquence de 10 minutes au lieu de 15 actuellement, soit 2 passages de plus par heure et par sens. L’augmentation du temps de fermeture serait « inacceptable ». Mais la question a-t-elle été posée-elle quand Ouigo a créé le Paris – Nantes via la Grande Ceinture ? Et si le trafic fret augmentait, faudrait-il réduire la desserte Versailles – Massy ?
Dans l’absolu, la ligne pourrait être exploitée en tram-train et gérée par l’atelier de Massy, mais elle ne fait pas partie du contrat attribué à RATP Cap Ile-de-France, comprenant T12 et T13. Il faudrait passer par un appel d’offres, sans certitude quant à son issue.
Autre obstacle : à défaut de nouvelles commandes, le marché Dualis va être prochainement fermé. Dommage pour l’objectif d’homogénéité de parc, quoi qu’on puisse penser des qualités – et défauts – de ce matériel.
Sud-Est : quel avenir pour la ligne S ?
Pour l’instant, le rétablissement de trains directs entre Paris, Corbeil-Essonnes, Malesherbes et Melun ne comporterait que 4 allers-retours par jour. S’il était possible et fiable de pouvoir aller plus loin, il faudra examiner le besoin en matériel roulant et l’ajout de Régio2N supplémentaires. L’arbitrage doit être cependant relativement rapide.
La rénovation des 43 MI2N de la RATP est un parcours du combattant. On n’a jamais vu un projet de cette consistance aussi lent puisque 7 ans après le lancement de l’opération, aucune rame n’a été remise en circulation.
Les MI2N devaient être remplacés à partir de 2035. Pour les MI09, la RATP prévoit une rénovation mi-vie très tardive, à partir de 2040. Conséquence, il semble difficile d’atteindre un jour l’unicité de parc sur le RER A. Il serait plus logique d’amorcer le traitement des MI09 dès 2030, avec un programme léger, pour construire un marché unique.
Il faudra aussi penser au remplacement du SACEM. Nous y revenons par la suite.
Et côté infrastructures ?
Délaissons la seule stratégie de parc pour aborder l’équipement de l’infrastructure et ses conséquences sur le matériel.
La modernisation de l’exploitation en Ile-de-France est un enjeu majeur. Il faudra d’abord définir l’outil : plutôt ERTMS ou plutôt CBTC (NExTEO) ? Il n’y a pas de réponse unique. Le CBTC n’est pas adapté à des lignes à mixité de circulation et ne peut être envisagé que sur des sections dédiées au seul trafic francilien. C’est par exemple le cas sur les groupes II et III de Saint-Lazare, avec par ricochet un besoin de coordination avec les choix post-SACEM du RER A. Mieux vaudrait n’avoir qu’un système, a minima sur le RER A et le groupe III. Cependant, l’exploitation réelle nécessite d’étendre le périmètre aux groupes II et IV du fait des équivalences d’itinéraires.
Cependant, il faut bien reconnaître que, pour le CBTC, NExTEO doit encore faire ses preuves : jusqu’à présent, le système suscite encore pas mal de suspicions et d’incertitudes. Quant à ERTMS, il faudra a minima un niveau 2 voire un niveau 3 pour être à la hauteur du défi, avec évidemment un pilotage automatique essentiel à l’amélioration de la capacité, de la performance et de la régularité de l’exploitation, via une homogénéisation du comportement des trains (suppression des disparités humaines de conduite).
Il faudra pour cela aussi continuer d’améliorer les installations de traction électrique : les matériels modernes tolérant moins les écarts de tension, surtout à la baisse, de nouvelles installations devront être ajoutées. On pense notamment à la section Melun – Moret – Montargis, où le bénéfice profiterait non seulement à la ligne R mais aussi aux trains régionaux et nationaux (Paris – Nevers et Paris – Clermont-Ferrand) qui ne seraient plus ralentis par les omnibus franciliens.
Sur le domaine 25 kV, quoique pas vraiment donné, le déplacement de certaines sections de séparation (on pense prioritairement à celle de Rosny-sous-Bois sur le RER E) devra être examiné pour ne pas casser les montées en vitesse. Le renforcement de plusieurs sous-stations s’impose aussi, pour suivre à la fois l’évolution des performances – et des contraintes – du matériel roulant que les besoins de l’exploitation : celle d’Asnières sur le réseau Saint-Lazare attend toujours une augmentation de puissance pourtant décidée depuis 2010.
Des évolutions dans la conception de l’exploitation
Cependant, il ne faudrait pas conditionner ces nouveaux horizons uniquement à la réalisation d’investissements importants. Ces nouveaux équipements devront être accompagnés d’une révision des pratiques d'exploitation qui, jusqu’à présent, ont plutôt réduit la capacité et la performance du réseau :
un déploiement du contrôle de vitesse par balise (KVB) assez restrictif,
une augmentation de 15 à 35 secondes du temps minimal de présentation de la voie libre dans la construction de l’horaire,
la vitesse sécuritaire en approche, préconisant d’être à 30 km/h au plus tard à 200 m d’un signal à l’avertissement (alors qu’il demande simplement d’être en mesure de s’arrêter au signal suivant),
et – liste non exhaustive – un encadrement des conducteurs pouvant être assez tatillon, avec pour conséquence la pratique de vitesses en-dessous du « trait » : en banlieue plus qu’ailleurs, rouler à 2 ou 3 km/h en-deçà de la vitesse autorisée peut avoir des conséquences sur la régularité.
Il faudra aussi actualiser les pratiques. Les nouveaux matériels sont quand même mieux armés et il serait possible de relever les coefficients d’accélération et de freinage dans le tracé des horaires. Transilien tracé à 0,6 m/s², ce qui assez peu en comparaison des 0,84 m/s² de la RATP. Même réflexion sur les temps de stationnement pour revenir à des valeurs de 30 à 40 secondes dans un grand nombre de gares… en concevant des trains dont le fonctionnement des portes soit efficace : de ce point de vue, le RERng est plutôt encourageant !
Première levée d'options pour la nouvelle génération de Citadis destinée aux lignes T1 et T8 : après les 37 rames de la tranche ferme, pour éliminer les TFS, Ile-de-France Mobilités commande 28 rames supplémentaires pour équiper l'extension à l'est, d'abord...
L'actualité des transports en commun de ce qui fut l'une des villes nouvelles de la région parisienne est assez riche. D'abord, le réseau fêtera ses 50 ans en mars prochain : la RATP avait alors créée chargée d'exploiter 5 lignes desservant l'agglomération...
Une ville nouvelle conçue autour des transports en commun
C’est un cas atypique en Ile-de-France. Les villes nouvelles n’ont pas été une réussite architecturale, fonctionnelle, humaine, économique et sociale. Elles ont été en quelque sorte des laboratoires de recherche à taille réelle d’une nouvelle forme d’aménagement urbain.
La ville nouvelle d’Evry, conçue en 1969, a été organisée autour d’une infrastructure de transport en commun en site propre d’une longueur de 17 km, autour de laquelle allaient être placés les équipements et fonctions de la cité. Le plan était coordonné également entre les réseaux de transport en commun : le tracé intégrait la desserte des 3 nouvelles gares de l’itinéraire Juvisy – Corbeil « par le plateau » construit parallèlement.
Conçue « en doigts de gant », l’objectif était d’atteindre une part de marché des transports en commun de 45 %, soit 3 fois plus que la moyenne nationale de l’époque, en plaçant 80 % de la population à moins de 400 m du tracé. Ce résultat était aussi lié au niveau de vie des habitants : le revenu moyen modeste sinon faible influe – à la baisse – sur le taux de motorisation des ménages et donc à la hausse sur l’utilisation des transports publics.
Utilisée par des autobus, le tracé du site propre a été conçu pour une solution plus lourde : on parlait à peine de tramway moderne – « métro léger » à l’époque – et l’hypothèse de trolleybus bimodes (RVI étudiait ce qui est devenu le PER180H en 1982) était avancée. Aujourd’hui encore, le tracé est aujourd’hui encore parfaitement compatible avec une solution ferrée.
Le site propre présente peu d’adhérences avec la circulation automobile, sauf à ses extrémités. Revers de la médaille, le site propre engendre une coupure urbaine assez nette, car il n’est pas forcément évident de la franchir, même à pied, selon la densité de passages inférieurs ou supérieurs.
Les premières lignes 401, 402, 403, 404 et 404N ont été mises en service en mars 1975. L’exploitation avait alors été confiée à la RATP. En janvier 1988, le service est confié à la nouvelle société d’économie mixte des Transports Intercommunaux Centre Essonne (TICE). Il dessert 24 communes avec 21 lignes.
L’exploitation du réseau désormais baptisé Evry Centre Essonne est depuis janvier 2024 assurée par les Transports Intercommunaux Seine Sénart Essonne (TISSE) filiale de Keolis.
Le réseau fait partie du lot n°23, incluant également 19 lignes d’autres réseaux (Seine Essonne, Cars Sœurs, certaines lignes Daniel Meyer…) impliquant une importante réorganisation de la production et de la gestion du matériel dans le cadre de cet appel d’offres concernant un lot important de l’univers Optile.
En 2024, le réseau utilise 139 autobus dont 66 articulés, 54 standards, 15 midibus et 4 minibus, gérés par 2 dépôts situés à Bondoufle et Corbeil-Essonnes.
Plusieurs projets concernent le territoire de l’agglomération d’Evry.
La création de T12
Mise en service en décembre 2023, cette quatrième ligne de tram-train, et la seule passant d’une voie ferrée nationale accueillant d’autres circulations à une infrastructure urbaine en voirie, apporte une nouvelle contribution à la desserte de l’agglomération – plus très – nouvelle. Ce premier maillon d’une tangentielle sud constitue ainsi une nouvelle branche du système de desserte en site propre, en direction de l’ouest.
Elle pourrait constituer la première phase d’un projet plus consistant qui viserait à parachever le projet initial : le site propre originel d’Evry a été conçu pour – disons cette fois le mot – un tramway.
Dans un premier temps cependant, le mode routier va être maintenu avec une « montée en gamme ».
TZen4 : amélioration de la ligne 402
C’est la ligne la plus fréquentée de toutes les lignes de grande couronne en Ile-de-France. Son succès ne se dément pas car la population continue d’augmenter de façon soutenue (+18 % de puis le début de la décennie).
Concernant la partie Gare de Corbeil-Essonnes – Viry-Chatillon La Treille de la ligne 402, le projet Tzen4 doit encore améliorer le service tout en restant en mode routier : un intervalle de 5 minutes en pointe, au maximum de 10 minutes en journée et l’introduction de mégabus bi-articulés (24 m) à traction électrique. Cette montée en gamme accompagne aussi plusieurs opérations de rénovation urbaine autour du trajet. La branche du Coudray-Monceaux sera donc exploitée de façon indépendante.
T12 et TZen4 seront en correspondance à deux reprises, à Grigny La Ferme Neuve et à la gare d’Evry-Courcouronnes. A la gare de Corbeil, TZen4 rejoindra l’actuel TZen1 venant de la gare de Lieusaint-Moissy.
Le choix d’un BHNS bi-articulé sur TZen4 laisse présager que l’option d’un tramway ne serait pas dénuée d’intérêt compte tenu de sa fréquentation.
Présentation par Van Hool des Exquicity bi-articulés avec rechargement par induction (système Alstom). Ultime évolution du mode bus pour l'actuelle ligne 402. (cliché Ile-de-France Mobilités)
Aller plus loin ?
La conversion de la ligne 402 en BHNS avec bus bi-articulés constitue l’ultime évolution capacitaire sans changer de mode de transport. Au-delà, il faudra passer au tramway. Avec une prévision de trafic de 47 000 voyageurs par jour, il serait d’ores et déjà pleinement justifié.
Plus largement, le site propre pourrait-il un jour accueillir le mode de transport auquel il était destiné ? L’hypothèse ne saurait être écartée. L’axe dominant serait une liaison entre Juvisy et Corbeil, assurant un cabotage que le RER D n’effectue que très partiellement. Les axes très routiers pourraient ainsi être requalifiés, à commencer par la RN7 dans la traversée de Viry-Châtillon et Ris-Orangis. Dans la traversée d’Evry, les sites propres existants pourraient être partiellement réutilisés.
En outre, le réseau est organisé autour d’un tronc commun d’orientation nord-sud, dont le potentiel de trafic est maximal mais dont les maillons contributeurs sont hétérogènes : comprendre qu’ils ne justifient pas individuellement une conversion au tramway.
Au-delà de la conversion du 402 / TZen4, le maillon nord-est du site propre, rejoignant la gare d’Evry Val de Seine pourrait compléter le dispositif, avec une antenne au sud au moins jusqu’au pôle universitaire.
Enfin, T12 pourrait être prolongé au moins jusqu’à la gare d’Evry – Génopôle voire au centre hospitalier pour améliorer la desserte de la ville nouvelle. De ce fait, toute réflexion sur le développement des tramways à Evry emporterait le choix du gabarit 2,65 m et de l’alimentation en 1500 V.
C'est assez paradoxal de se poser cette question alors que le passage à la signalisation en cabine avec pilotage automatique va être étendu sur la branche de Chessy du RER A jusqu'à la gare de Noisy-Champs. Néanmoins, le Système d'Aide à la Conduite,...
D’un montant de 55 M€, l’opération « avant Jeux Olympiques » de la gare du Nord est achevée. Loin du projet de complexe commercial finalement retoqué, les investissements réalisés ont pour objectif d’améliorer la capacité et les circulations dans les...
Jamais dans l’histoire du métro parisien n’avait été mise en service une nouvelle section aussi longue : 14 km, sans oublier les 1700 m supplémentaires au nord. Le précédent « record » remonte… au 19 juillet 1900. C’est dire.
Une ligne olympique
Ce 24 juin 2024, la ligne 14 a donc été prolongée au nord de la mairie de Saint-Ouen à Saint-Denis Pleyel, et au sud du quartier des Olympiades à l’aéroport d’Orly. Cependant, avec 30,2 km, elle ne détrône pas en longueur la ligne 2 à Lille, qui, avec ses 32 km, ne devra céder sa place qu’à la ligne 15 du Grand Paris Express, dont la première section atteindra 33 km.
Ces deux tronçons ont été menés à un rythme effréné, quitte à imposer d’importantes perturbations aux voyageurs pour procéder au raccordement et aux essais des nouvelles installations et du nouveau système de pilotage automatique : il y aura forcément un examen a posteriori à mener pour étudier des solutions moins pénalisantes, que les voyageurs des lignes 4 et 11 ont aussi subi pour des raisons similaires.
C’est aussi le véritable lancement du Grand Paris Express puisque la ligne 14, bien que restant sous maîtrise d’ouvrage et exploitation de la RATP, est intégrée à ce projet pharaonique. Seuls les deux terminus ont été confiés à la Société du Grand Paris.
Il faut aussi ajouter la mise en service d’un autre ouvrage hors norme : le Franchissement Urbain de Pleyel, dont la première partie piétonne relie la station de la ligne 14 à celle du RER D (Stade de France – Saint-Denis) en enjambant les 48 voies du faisceau ferroviaire.
Il fallait bien cela, puisque c’est à peu près la seule grande nouveauté en matière de transports en commun qui a finalement réussi à être livrée avant les Jeux Olympiques. CDG Express et la ligne 15 devront attendre encore au moins une année supplémentaire.
Un projet majeur pour les franciliens
Il n’est cependant pas exagéré de considérer que l’enjeu majeur de la ligne 14 réside au sud, en créant un nouvel axe de grande capacité entre le RER B, la ligne 7 (jusqu’à Villejuif) et le RER C. La desserte de l’aéroport d’Orly constitue à n’en pas douter l’autre changement majeur à l’échelle de l’Ile-de-France, même si son accès sera, pour les utilisateurs occasionnels, assujettie à un tarif particulier et d’acquisition pas forcément facile puisque incompatible avec certains pass Navigo occasionnels. Cependant, l’accès direct à l’Institut Gustave Roussy (quand la station sera terminée) et l’amélioration de l’accès aux emplois du secteur Orly – Rungis sont des points non négligeables.
Au nord, c’est un peu différent et, après les Jeux Olympiques, la nouvelle station ne prendra réellement son envol qu’avec l’arrivée des lignes 15, 16 et 17. C’est quand même une alternative de taille au RER D pour l’accès à La Plaine-Saint-Denis, voire au Stade de France, quoique celui-ci se situe à environ 20 minutes à pied.
La prévision de trafic donne le vertige : un million de voyageurs par jour. C’est unique en Europe et il faut aller en Asie pour trouver des scores au moins équivalents. Cependant, même avec des trains de 120 m de long, le gabarit 2,40 m hérité du réseau historique (un choix lié aux origines à la stratégique d’acquisition du matériel roulant) ne sera pas avare en contraintes, notamment par la cohabitation avec les voyageurs à destination de l’aéroport et leurs bagages. Certes, l’intervalle de 85 secondes devrait assurer un flux continu avec plus de 39 000 places par heure et par sens à ce niveau de service, mais il est indéniable qu’avec la charge actuelle dans Paris, les atouts de ce prolongement vont mobiliser pleinement cette capacité.
Des stations ou des gares ?
L’autre changement – et de taille – de ce prolongement réside dans la conception des stations, d’une toute autre dimension que ce qu’on a pu connaître jusqu’à présent, même avec celles de l’extension pourtant récente à Saint-Ouen. Cette rupture se manifeste évidemment par une architecture fastueuse, résultat de la mobilisation de grands architectes. Il faudra quand même évaluer dans la durée l’entretien de ces constructions parfois audacieuses, certes très spacieuses, et son coût.
Cependant, au-delà des bâtiments d’accès, les carrossages métalliques et le béton à nu n’ont pas totalement disparu. Cependant, seules Saint-Denis Pleyel et Aéroport d’Orly se distinguent réellement des autres créations. Les aménagements ne sont pas totalement finis, comme c’est désormais l’habitude : cela concerne essentiellement des finitions et quelques habillages de murs, comme à Chevilly-Larue.
Autre point concernant les stations : leur dénomination n’est pas précise. La ligne 14 connaît déjà un cas, avec la station « Saint-Ouen ». C’est flou. Il est vrai que, hormis dans Paris, le métro ne mentionne jamais les gares (exemple à La Défense). Il est peut-être temps d’innover et de rebaptiser cette station « Gare de Saint-Ouen ».
Le terminus Saint-Denis Pleyel n’est pas en correspondance avec la ligne 13, sinon par un cheminement en voirie.
Au sud, les stations L’Haÿ-les-Roses, Chevilly-Larue et Thiais-Orly ne localisent pas précisément leur emplacement :
la première est assez à l’écart de la ville, et quasiment en limite de Chevilly-Larue ;
la deuxième est au droit de la station Porte de Thiais de la ligne T7 ;
la troisième est à proximité de la gare du RER C du Pont de Rungis.
Les trains relient les deux terminus en 40 minutes soit 40,5 km/h de moyenne. On a pu noter quelques coups de freins ponctuels, en pleine ligne, au droit de certains appareils de voie. Seule la section Olympiades – Maison Blanche est parcourue à moindre allure, car l’interstation est courte et en courbe plus prononcée.
En ligne, le comportement des MP14 peut être étonnant : les attaques de courbes peuvent être assez brutales, plus que sur la section préexistante et le roulement est plus irrégulier encore. C’est curieux (et le constat a été fait sur plusieurs rames). Le roulement sur pneumatiques parvient réellement à ses limites, car on a l’impression qu’il est un frein à la vitesse sur ce parcours. La comparaison avec la première section de la ligne 15, à roulement fer et apte à 110 km/h, devrait la confirmer.
Difficile d’aller plus loin après 3 jours d’exploitation. Tout au plus peut-on noter que la fréquentation au sud d’Olympiades est pour l’instant assez modeste, comme le prolongement à Saint-Ouen fin 2020. L’affluence peut être irrégulière, surtout au départ d’Orly, en fonction des horaires d’arrivée des vols. Sans compter un premier pépin technique significatif…
C’est après les Jeux Olympiques qu’un premier bilan pourra être effectué sur cette première étape du Grand Paris Express pour les franciliens.
Connexion
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