Intel’s next-generation Core Ultra laptop chips finally have a launch date: September 3^rd.

Codenamed Lunar Lake, Intel has been touting the chips for nearly a year now. Most recently, Intel offered the press a deep dive briefing on the chips and their underlying architectures at Computex back in June, along with a public preview during the company’s Computex keynote. At the time Intel was preparing for Q3’2024 launch, and that window has finally been narrowed down to a single date – September 3^rd – when Intel will be hosting their Lunar Lake launch event ahead of IFA.

Intel’s second stab at a high volume chiplet-based processor for laptop users, Lunar Lake is aimed particularly at ultrabooks and other low-power mobile devices, with Intel looking to wrestle back the title of the most efficient PC laptop SoC. Lunar Lake is significant in this respect as Intel has never previously developed a whole chip architecture specifically for low power mobile devices before – it’s always been a scaled-down version of a wider-range architecture, such as the current Meteor Lake (Core Ultra 100 series). Consequently, Intel has been touting that they’ve made some serious efficiency advancements with their highly targeted chip, which they believe will vault them over the competition.

All told, Lunar Lake is slated to bring a significant series of updates to Intel’s chip architectures and chip design strategies. Of particular interest is the switch to on-package LPDDR5X memory, which is a first for a high-volume Core chip. As well, Lunar Lake incorporates updated versions of virtually every one of Intel’s architecture, from the CPU P and E cores – Lion Cove and Skymont respectively – to the Xe2 GPU and 4^th generation NPU (aptly named NPU 4). And, in a scandalous twist, both of the chiplets/tiles on the CPU are being made by TSMC. Intel isn’t providing any of the active silicon for the chip – though they are providing the Foveros packaging needed to put it together.

Suffice it to say, no matter what happens, Lunar Lake and the Core Ultra 200 series should prove to be an interesting launch.

It’s worth noting, however, that while Intel’s announcement of their livestreamed event is being labeled a “launch event” by the company, the brief reveal doesn’t make any claims about on-the-shelves availability. September 3^rd is a Tuesday (and the day after a US holiday), which isn’t a typical launch date for new laptops (for reference, the lightly stocked Meteor Lake launch was a Thursday). So Intel’s launch event may prove to be more of a soft launch for Lunar Lake; we’ll have to see how things pan out in the coming weeks.

Continuing our ongoing look at the latest-generation ATX 3.1 power supplies, today we are examining Cooler Master's V Platinum 1600 V2, a recent addition to the company's expansive PSU lineup.

The V Platinum 1600 V2 is designed to cater to top-end gaming and workstation PCs while offering maximum compatibility with modern ATX directives. And while it boasts a massive 1600 Watt output and a long list of features, the V is a workhorse of a power supply rather than a flagship; Cooler Master is aiming the PSU at budget-conscious users who can't justify spending top dollar, but whom none the less need a powerful and relatively efficient (80PLUS Platinum) power supply.

So often we see PSU vendors go for broke on their high-wattage units, since there's a lot of overlap there with the premium market, so it will be interesting to see what Cooler Master can do with a slightly more modest bill of materials.

Micron on Tuesday announced that the company has begun shipping its 9th Generation (G9) 276 layer TLC NAND. The next generation of NAND from the prolific memory maker, Micron's latest NAND is designed to further push the envelope on TLC NAND performance, offering significant density and performance improvements over its existing NAND technology.

Micron's G9 TLC NAND memory features 276 active layers, which is up from 232-layers in case of Micron's previous generation TLC NAND. At this point the company is being light on technical details in their official material. However in a brief interview with Blocks & Files, the company confirmed that their 276L NAND still uses a six plane architecture, which was first introduced with the 232L generation. At this point we're assuming Micron is also string-stacking two decks of NAND together, as they have been for the past couple of generations, which means we're looking at 138 layer decks.

On the density front, Micron told Blocks & Files that they have improved their NAND density by 44% over their 232L generation. Which, given what we know about that generation, would put the density at around 21 Gbit/mm². Or for a 1Tbit die of TLC NAND, that works out to a die size of roughly 48.9mm², comparable to the die size of a 512Gbit TLC die from Micron's older 176L NAND.

Besides improving density, the other big push with Micron's newest generation of NAND was further improving its throughput. While the company's 232L NAND was built against the ONFi 5.0 specification, which topped out at transfer rates of 2400 MT/sec, their new 276L NAND can hit 3600 MT/sec, which is consistent with the ONFi 5.1 spec.

Meanwhile, the eagle-eyed will likely also pick up on Micron's ninth-generation/G9 branding, which is new to the company. Micron's has not previously used this kind of generational branding for their NAND, which up until now has simply been identified by its layer count (and before the 3D era, its feature size). Internally, this is believed to be Micron's 7th generation 3D NAND architecture. However, taking a page from the logic fab industry, Micron seems to be branding it as ninth-generation in order to keep generational parity with its competitors, who are preparing their own 8th/9th generation NAND (and thus cliam that they are the first NAND maker to ship 9th gen NAND).

And while this NAND will eventually end up in all sorts of devices – including, no doubt, high-end PCIe Gen5 drives thanks to its high transfer rates – Micron's launch vehicle for the NAND is their own Micron 2650 client SSD. The 2650 is a relatively straightforward PCIe Gen4 x4 SSD, using an unnamed, DRAMless controller alongside Micron's new NAND. The company is offering it in 3 form factors – M.2 2280, 2242, and 2230 – with a modest set of capacities ranging from 256GB to 1TB.

Micron's 2650 NVMe SSDs offer sequential read performance of up to 7000 MB/s as well as sequential write performance of up to 6000 MB/s. As for random performance, we are talking about up to a million read and write IOPS, depending on the configuration.

The performance of the drives scales pretty significantly with capacity, underscoring how much parallelism is needed to keep up with the PCIe Gen4 controller. The rated capacity of the drives scales similarly, with the smallest drive rated for 200TBW (800 drive writes), while the largest drive is rated for 600 TBW (600 drive writes).

“The shipment of Micron G9 NAND is a testament to Micron’s prowess in process technology and design innovations,” said Scott DeBoer, executive vice president of Technology and Products at Micron. “Micron G9 NAND is up to 73% denser than competitive technologies in the market today, allowing for more compact and efficient storage solutions that benefit both consumers and businesses.”

Micron's G9 276-layer TLC NAND memory is also in qualification with customers in component form, so expect the company's partners to adopt it for their high-end SSDs in the coming quarters. In addition, Micron plans Crucial-branded SSDs based on its G9 NAND memory..

Although AMD delayed launch of its Ryzen 9000-series processors based on the Zen 5 microarchitecture from July 31, to early and mid-August, the company's partner (and major US retailer) Best Buy briefly began listing the new CPUs today, revealing a very plausible set of launch prices. As per the retailer's product catalog, the most affordable unlocked Zen 5-based processor will cost $279, whereas the highest-performing Zen 5-powered CPU will cost $599 at launch.

AMD will start its Ryzen 9000 series rollout from relatively inexpensive six-core Ryzen 5 9600X and eight-core Ryzen 7 9700X on August 8. Per the Best Buy listing, the Ryzen 5 9600X will cost $279, whereas the Ryzen 7 9700X will carry a recommended price tag of $359.  Meanwhile, The more advanced 12-core Ryzen 9 9900X and 16-core Ryzen 9 9950X will hit the market on August 15 at MSRPs of $449 and $599, respectively, based on the Best Buy listing.

It is noteworthy that when compared to the launch prices of the Zen 4-based Ryzen 7000 processors, the new Zen 5-powered Ryzen 9000 CPUs come in cheaper. The range topping Ryzen 9 5950X started at $799 in 2020, while the Ryzen 9 7950X had a recommended $699 price tag in 2022. By contrast, the top-end Ryzen 9 9950X is listed at $599. Both Ryzen 7 5600X and Ryzen 7 7600X cost $299 at launch, while the upcoming Ryzen 5 9600X will apparently be priced at $279 at launch.

As always with accidental retailer listings, it should be emphasized that AMD has not yet announced official pricing for their Ryzen 9000 CPUs. Given Best Buy's status as one of the largest US electronics retailers, these prices carry a very high probability of being accurate; but none the less, they should be taken with a grain of salt – if only because last-minute price changes are not unheard of with new CPU launches.

Source: Best Buy (via @momomo_us)

Amidst the backdrop of a weak quarterly earnings report that saw Intel lose money for the second quarter in a row, Intel today has announced that the company will be cutting costs by $10 billion in 2025 in an effort to bring Intel back to profitability. The cuts will touch almost every corner of the company in some fashion, with Intel planning to cut spending on R&D, marketing, administration, and capital expenditures. The most significant of these savings will come from a planned 15% reduction in force, which will see Intel lay off 15,000 employees over the next several months – thought to be one of Intel’s biggest layoffs ever.

In an email to Intel’s staff, which was simultaneously published to Intel’s website, company CEO Pat Gelsinger made the financial stakes clear: Intel is spending an unsustainable amount of money for their current revenues. Citing the company’s current costs, Gelsinger wrote that “our costs are too high, our margins are too low,“ and that “our annual revenue in 2020 was about $24 billion higher than it was last year, yet our current workforce is actually 10% larger now than it was then.” Consequently, Intel will be enacting a series of painful cuts to bring the company back to profitability.

Intel is not publicly disclosing precisely where those cuts will come from, but in the company’s quarterly earnings release, the company noted that it was targeting operating expenses, capital expenditures, and costs of sales alike.

For operating expenses, Intel will be cutting “non-GAAP R&D and marketing, general and administrative” spending, with a goal to trim that from $20 billion in 2024 to $17.5 billion in 2025. Meanwhile gross capital expenditures, a significant expense for Intel in recent years as the company has built up its fab network, are projected to drop from $25 billion to $27 billion for 2024, to somewhere between $20 billion and $23 billion in 2025. Compared to Intel’s previous plans for capital expenditures, this would reduce those costs by around 20%. And finally, the company is expecting to save $1 billion on the cost of sales in 2025.

Separately, in Intel’s email to its employees, Gelsinger outlined that these cuts will also require simplifying Intel’s product portfolio, as well as the company itself. The six key priorities for Intel will include cutting underperforming product lines, and cutting back Intel’s investment in new products to “fewer, more impactful projects”. Meanwhile on the administrative side of efforts, Intel is looking to eliminate redundancies and overlap there, as well as stopping non-essential work.

• Reducing Operational Costs: We will drive companywide operational and cost efficiencies, including the cost savings and head count reductions mentioned above.
• Simplifying Our Portfolio: We will complete actions this month to simplify our businesses. Each business unit is conducting a portfolio review and identifying underperforming products. We are also integrating key software assets into our business units so we accelerate our shift to systems-based solutions. And we will narrow our incubation focus on fewer, more impactful projects.
• Eliminating Complexity: We will reduce layers, eliminate overlapping areas of responsibility, stop non-essential work, and foster a culture of greater ownership and accountability. For example, we will consolidate Customer Success into the Sales, Marketing and Communications Group to streamline our go-to-market motions.
• Reducing Capital and Other Costs: With the completion of our historic five-nodes-in-four-years roadmap clearly in sight, we will review all active projects and equipment so we begin to shift our focus toward capital efficiency and more normalized spending levels. This will reduce our 2024 capital expenditures by more than 20%, and we plan to reduce our non-variable cost of goods sold by roughly $1 billion in 2025.
• Suspending Our Dividend: We will suspend our stock dividend beginning next quarter to prioritize investments in the business and drive more sustained profitability.
• Maintaining Growth Investments: Our IDM2.0 strategy is unchanged. Having fought hard to reestablish our innovation engine, we will maintain the key investments in our process technology and core product leadership.

The bulk of these cuts, in turn, will eventually come down to layoffs. As previously noted, Intel is planning to cut about 15% of its workforce. Just how many layoffs this will entail remains to be seen; Gelsinger’s letter puts it at roughly 15,000 employees, while Intel’s most recent published headcount would put this figure at closer to 17,000 employees.

Whatever the number, Intel is expecting to have most of the reductions completed by the end of this year. The company will be using a combination of early retirement packages and buy-outs, or what the company terms as “an application program for voluntary departures.”

Intel’s investors will be taking a hit, as well. The company’s generous quarterly dividend, a long-time staple of the chipmarker and one of the key tools to entice long-term investors, will be suspended starting in Q4 of 2024. With Intel losing money over multiple quarters, Intel cannot afford (or at least, cannot justify) paying out cash in the forms of dividends when that money could be getting invested in the company itself. Though as the long-term health of the company is still reliant on offering dividends, Intel says that the suspension will be temporary, as the company reiterated its “long-term commitment to a competitive dividend as cash flows improve to sustainably higher levels.” For Q2 2024, Intel paid out $0.125/share in dividends, or a total of roughly $0.5B.

Ultimately, the message coming from Intel today is that it is continuing (if not accelerating) its plans to slim down the company; to focus on a few areas of core competencies that suit the company’s abilities and its financial goals. Intel is throwing everything behind its IDM 2.0 initiative to regain process leadership and serve as a world-class contract foundry, and even with Intel’s planned spending cuts for 2025, that initiative will continue to move forward as planned.

On that note, cheering up investors in what’s otherwise a brutal report from the company, Intel revealed that they’ve achieved another set of key milestones with their in-development 18A process. The company released the 1.0 process design kit (PDK) to customers last month, and Intel has successfully powered-on their first Panther Lake and Clearwater Forest chips. 18A remains on track to be “manufacturing-ready” by the end of this year, with Intel looking to start wafer production in the first half of 2025. 18A remains a make-or-break technology for Intel Foundry, and the company as a whole, as this is the node that Intel expects to return them to process leadership – and from which they can improve upon to continue that leadership.

Sources: Intel Q2'24 Earnings, Intel Staff Letter

Update 08/02: Patrick Moorhead has published a further tweet, clarifying that "Pat [Gelsinger] didn’t tell me l that there were yield issues. This was *my* interpretation." The text of the article has been updated accordingly to reflect this tweet, as well as Intel statements about accelerating their Ireland Fab 34 ramp-up.

Alongside Intel’s weak Q2 2024 earnings report and the announcement of $10 billion in spending cuts and layoffs for 2025, the company is also disclosing some new information about their chip deliveries over the first half of the year. A brief report, posted on X by analyst Patrick Moorhead and citing a conversation with Intel CEO Pat Gelsinger, revealed that Intel encountered a major production bottleneck on Meteor Lake earlier this year. The issue was significant enough to drive intel to take the extraordinary and costly step of accelerating their Ireland fab ramp-up in order to improve chip capacity.

It was a very rough Q2 for $INTC. And that guide... Thanks, @Pgelsinger, for the time to discuss.

It appears that there were yield/throughput issues on Meteor Lake, negatively impacting gross margins. When you have to get the product to your customers, and you have wafers to… pic.twitter.com/pHU66xvFe7

— Patrick Moorhead (@PatrickMoorhead) August 1, 2024

In a separate tweet posted several hours later, Moorhead then clarified that the yield issues mentioned in his first tweet were his interpretation of the matter, rather than something Pat Gelsinger had told him directly.

Decoding Moorhead’s dense tweets, fundamentally, Moorhead is questioning why Intel's Cost of Goods Sold (COGS) – how much the company's chips cost to produce – were on the rise with the launch of Meteor Lake.  The analyst surmised that yields and/or some other unexpected production bottleneck must be the case, as these are the typical issues that drive up chip COGS on a short-term basis like Intel has been experiencing.

And, judging from Intel's earnings call that took place after the initial tweet, Moorhead was right to an extent. Referencing the increased COGS, Intel CFO David Zinsner noted that Intel opted to ramp up its high-volume production in Ireland faster than initially planned. This increased Intel's capacity for Intel 4 (and Intel 3) capacity, but doing so also increased their costs, as wafers out of Ireland cost more in the near term.

Between Moorhead's report that OEMs have been receiving fewer Meteor Lake chips than they could use, and Intel's announcement that they accelerated the Ireland fab ramp-up, this is the first significant disclosure that Meteor Lake chips were, at least at some point, in unexpectedly short supply. Which in turn required Intel to take unexpected and extraordinary steps in order to improve chip production, at the cost of lower short-term profit margins and higher COGS.

The first of Intel's high-volume manufacturing (HVM) fabs to be equipped for the Intel 4 and Intel 3 processes, Fab 34 in Ireland is a critical element to Intel's cutting-edge product plans over the next couple years. Intel was not initially planning on relying so much on Fab 34 this soon – instead using their Oregon development fabs to do more of their Intel 4 & Intel 3 fabrication – but the company opted to ramp up at a faster pace. The benefit to Intel is that they get more fab capacity sooner, but it means they're incurring around $1 billion in costs now of what would have otherwise been spread out over further quarters during a more gradual ramp-up.

The net result was that, while Intel took a margin hit, it also allowed them to supply more Meteor Lake chips than they otherwise would have, even beating their own previous projections for Q2 shipments. Overall, Intel reported in their Q2 earnings that they’ve shipped 15 million “AI PC” chips since Meteor Lake’s launch, though the company doesn't break down how many of those were in Q2 versus Q1 and Q4'23. Still, according to Moorhead, this was fewer chips than OEMs would have liked to have, and they would have taken more chips if they were available.

COGS and Ireland ramp-ups aside, Moorhead also posits that some of Intel's capacity boost came from running “hot lots” of Meteor Lake – high priority wafer batches that get moved to the front of the line in order to be processed as soon as possible (or as reasonably close as is practical). Hot lots are typically used to get highly-demanded chips produced quickly, getting them through a fab sooner than the normal process would take. As a business tool, hot lots are a fact of life of chip production, but they’re undesirable because in most cases they cause disruptions to other wafers that are waiting their turn to be processed.

If true, running hot lots of Meteor Lake would be a significant development given the potential disruptions. At the same time, however, the situation with Meteor Lake is somewhat particular, as the Intel 4 process used for Meteor Lake’s compute tile (the only active tile made at Intel) is not offered to external foundry customers, or even used by other Intel CPUs (Xeon 6s all use Intel 3). So hot lots of Meteor Lake would have few other wafers to even jump ahead of for EUV tooling (Intel would certainly not put them ahead of high-margin Xeon products), while it's unclear how this would cascade down to any tools shared with Intel 7.

Intel, for their part, did not comment on Meteor Lake chip yields or hot lots in their earnings call.

In any case, Intel at this point is looking to turn around their troubled fortunes in the second half of this year. The company’s next-gen client SoC for mobile, Lunar Lake, is set to launch on September 3^rd. And notably, both of its active tiles are being built by TSMC. So Lunar Lake would be spared from any Intel logic fab bottlenecks, though it still has to go through Intel’s facilities for assembly using their Foveros technology. And there remains the thorny issue of higher production costs altogether, since Intel is paying for what's effectively the fully outsourced production of a Core CPU.

Update 08/06: Intel published an additional note on Monday, confirming which SKUs are covered by the program. The full list of SKUs has been added to the article below, but it's essentially the 13600K/14600K and above – all of Intel's high-TDP desktop parts using the Raptor Lake B0 die.

Capping off an extensive (and expensive) week for Intel, the company has also announced that they are taking additional steps to address the ongoing chip stability issues with desktop Raptor Lake chips – the 13^th and 14^th Generation desktop Core processors. In order to keep owners whole, Intel will be extending the warranty on retail boxed Raptor Lake chips by two years, bringing the cumulative warranty for the chips to five years altogether.

This latest announcement comes as Intel is still in the process of preparing their major Raptor Lake microcode update, which is designed to mitigate the issue (or rather, further damage) by fixing the elevated voltage bug in their existing microcode that has led to the issue in the first place. That microcode update remains scheduled for mid-August, roughly a couple of weeks from now.

But until then – and depending on how quickly the update is distributed, even afterwards – there is still the matter of what to do with Raptor Lake desktop chips that are already too far gone and are consequently unstable. Intel’s retail boxed Raptor Lake chips ship with a 3 year warranty, which given the October 2022 launch date, would have the oldest of these chips covered until October of 2025 – a bit over a year from now. And while the in-development fix should mean that this is plenty of time to catch and replace any damaged chips, Intel has opted to take things one step further by extending the chips’ warranty to five years.

Overall, this is much-needed bit of damage control by Intel to restore some faith in their existing Raptor Lake desktop processor lineup. Even with the planned microcode fix, it remains unclear at best about what the long-term repercussions of the voltage bug is, and what it means for the lifespan of still-stable chips that receive the fixed microcode. In the best-case scenario, an extended warranty gives Raptor Lake owners a bit more peace of mind, and in a worst-case scenario, they’re now covered for a couple of years longer if the chip degradation issues persist.

One important thing to note, however, is that the extended warranty will only apply to boxed processors, i.e. Intel’s official retail chips. Intel’s loose chips that are sold by the tray to OEMs and certain distributors – commonly referred to as “tray” processors – are not covered by the extended warranty. While Raptor Lake tray processors do technically come with a three-year warranty of their own, Intel does not provide direct, end-user warranty service for these chips. Instead, those warranties are serviced by the OEM or distributor that sold the chip.

With the bulk of Intel’s chips going to OEMs and other professional system builders, Intel will undoubtedly need to settle things with those groups, as well. But with OEM dealings typically remaining behind closed doors, it’s unlikely we’ll hear about just what is agreed there. Regardless, whatever Intel does (or doesn’t do) to assuage OEMs and distributors, those groups will remain responsible for handling warranty claims for tray chips.

Finally, it should be noted that while today’s announcement outlines the two-year warranty extension, it doesn’t deliver the full details on the program. Intel expects to release more details on the extended warranty program “in the coming days.”

Intel’s full statement is below:

On Monday, Intel published an additional post outlining the specific SKUs covered by the extended warranty program. As the voltage/instability issues are thought to only affect high-TDP chips using Intel's Raptor Lake B0 die, which was used for both the 13th Gen and 14th Gen Core processors, the extended warranty program is also being setup to cover those processors specifically. In other words, only chips that are capable of being affected by the issue are receiving the extended warranty.

The rest of Intel's messaging is essentially unchanged from last week, telling customers of boxed processors to contact Intel directly, while tray processor owners need to contact their retailer/OEM.

Additional Details on Via Oxidation Issue

Separately, Intel’s community team also posted a brief update on the via oxidation issue that, although distinct from the current Raptor Lake instability issues, came into question at roughly the same time. Intel has previously stated that that issue is unconnected to the ongoing stability issues, and was fixed back in 2023. And this latest update offers a few more details on just what that manufacturing issue entailed.

The trend towards miniaturization of desktop systems was kickstarted by the Intel NUCs in the early 2010s. The increasing popularity of compact PCs also led to the introduction of a variety of slightly larger form-factors. Custom boards falling in size between the NUC's 4" x 4" ultra-compact form-factor (UCFF) and industrial-applications oriented 3.5" SBC have also gained traction. The ECS LIVA Z5 PLUS is one such system, designed and marketed towards business and industrial use-cases.

Intel's Raptor Lake series of products was introduced in early 2023. It came in both P and U versions for notebooks and ultraportables, in addition to the usual H(X) ones for high-performance gaming notebooks. Most mini-PCs and NUCs opted for the P varieties in their systems. The ECS LIVA Z5 PLUS represents a different take, with a U series processor operating with a slight increase in the configurable TDP (cTDP) over Intel's suggested 15W operating point. Read on for a comprehensive look at the performance and features of the ECS LIVA Z5 PLUS, including some comments on the benefits enabled by the slightly larger form-factor.

In an unexpected announcement during their quarterly earnings call this week, Western Digital revealed that it has begun sampling an upcoming 32TB hard drive. The nearline HDD is aimed at hyperscalers, and relies on a combination of Westen Digital's EAMR technology, as well as shingled magnetic recording (SMR) technology to hit their highest capacity figures to date.

Western Digital's 32TB HDD uses all of the company's most advanced technologies. Besides energy-assisted magnetic recording (EAMR/ePMR 2 to be more precise) technology, WD is also leveraging triple-stage actuators for better positioning of heads and two-dimensional (TDMR) read heads, OptiNAND for extra performance and reliability, distributed sector (DSEC) technology and a proprietary error correcting code (ECC) technology. And, most importantly, UltraSMR technology to provide additional capacity.

"We are shipping samples of our 32TB UltraSMR/ePMR nearline hard drives to select customers," said David Goeckeler, chief executive of Western Digital, at the earnings call. "These drives feature advanced triple-stage actuators and OptiNAND technology which are designed for seamless qualification, integration and deployment in hyperscale cloud and enterprise data centers while maintaining exceptional reliability."

Seagate is currently shipping its 30TB Exos HDDs based on heat-assisted magnetic recording (HAMR) platform called Modaic 3+ to select exascalers, and the company has implied that it can build a 32TB version of the drive using SMR. Therefore, from capacity point of view, Western Digital's announcement means that the company has caught up with its rival.

As with the comapny's other UltraSMR drives, the 32TB nearline drive is aimed at WD's enterprise customers, whose infrastructure can handle the additional management requirements that SMR imposes. As SMR in enterprise drives is not transparent, it's up to the host to manage many of the complexities that come with a hard drive that isn't suited for random writes. Though at least in WD's case, the upshot is that UltraSMR also offers a more significant density increase than other SMR implementations, using a larger number of SMR bands to increase HDD capacity by up to 20%.

Working backwards, that 20% capacity increase also means that WD's new drive is starting from 2.56TB CMR platters. And while 2.56TB makes for a very decent areal density, this would mean that WD is still behind rival Seagate in terms of areal density overall, as Seagate has 3TB CMR platters in its latest HAMR-based Exos drives.

Samsung is announcing today that it has begun mass production of 12 GB and 16 GB LPDDR5X modules in the industry's thinnest package. Samsung's shrunken memory packages measure approximately 0.65 mm in thickness, making them 0.06 mm (~9%) thinner than standard LPDDR5X packages. The company expects the new DRAM devices to be used to make for thinner smartphones, or improve their performance by enabling better airflow inside.

According to the company's press release, Samsung achieved this ultra-thin design by employing new packaging methods, such as optimized printed circuit boards (PCBs) and epoxy molding compound (EMC). Additionally, an optimized back-lapping process was used to further reduce the height of the packages. The newly developed DRAM packages are not only thinner by 9% compared to previous models but also offer a 21.2% improvement in heat resistance. 

Thinner LPDDR5X packaging help enhance airflow within smartphones, significantly improving thermal management, which means higher performance and longer battery life. Also, better thermal management help to prolong device's lifespan.

"Samsung's LPDDR5X DRAM sets a new standard for high-performance on-device AI solutions, offering not only superior LPDDR performance but also advanced thermal management in an ultra-compact package," said YongCheol Bae, Executive Vice President of Memory Product Planning at Samsung Electronics. "We are committed to continuous innovation through close collaboration with our customers, delivering solutions that meet the future needs of the low-power DRAM market."

While Samsung's thinner LPDDR5X DRAM packages contribute to making smartphones slimmer, they are just one part of the overall design strategy. Other components, such as thinner protective glass, PCBs, and batteries, play considerably more significant roles in reducing device thickness. Meanwhile, the primary benefit of these new memory modules may be in improving airflow inside smartphones.

Samsung is looking to further expand its LPDDR5X product lineups by developing even more compact packages, including 6-layer 24 GB and 8-layer 32 GB modules. Specific details about the thickness of these future memory modules have not yet been disclosed, though making high-capacity DRAMs thinner in general is an important thing.

Solidigm's datacenter SSD lineup includes models targeting different performance, endurance, and cost tradeoffs. Last year, the company had introduced the D5-P5336 QLC drive as a low-cost high-capacity drive for read-heavy workloads, while also preparing the SLC-based D7-P5810 for extremely write-intensive workloads requiring high endurance. The D7-P5520 / D7-P5620 Gen 4 drives with Solidigm's own 144L 3D TLC have been the high-performance offerings for generic workloads over the last couple of years.

Solidigm is announcing the availability of the successor to the D7-P5x20 today - the new D7-PS1010 and D7-PS1030. Both of these NVMe drives use SK hynix's 176L 3D TLC NAND and come with a PCIe 5.0 interface. The third digit in the model number matches the DWPD rating, with the D7-PS1010 targeting mixed workloads with a 1 DWPD rating, and the D7-PS1030 targeting write-intensive use-cases with a 3 DWPD rating.

Compared to the previous generation D7-P5x20, the D7-PS10x0 series brings about the following upgrades:

• Move from PCIe 4.0 x4 to PCIe 5.0 x4
• Move from 144L floating gate 3D TLC (Solidigm) to 176L charge trap 3D TLC (SK hynix)
• 25% longer mean-time between failures (MTBF) at 2.5M hours
• 10x higher uncorrectable bit-error rate (UBER) at 1E-18
• 1.8x to 2.8x improvement in high queue-depth random access IOPS
• 2.0x to 2.2x improvement in high queue-depth sequential access throughput

The specifications of the two new SSD families are summarized in the table below.

Based on Solidigm's own internal testing, the D7-PS1010 compares very favorably against the Gen 5 datacenter SSDs already in the market from Samsung and Kioxia. However, the recently introduced Micron 9550 series may present a better challenge to Solidigm's claims.

Gen 5 SSDs are well-suited for the storage-intensive tasks in AI workloads. Every new product needs to tie itself to the AI buzzword currently, but we should excuse SSD manufacturers for doing the same - after all training and inference needs to move large amounts of data back and forth between the processing engine and underlying memory. Solidigm expects the D7-PS10x0 to be a good fit as direct-attached storage internal to GPU servers or as all-flash tier supporting a HDD-only object tier in the cloud. For on-premises GPU servers, the flash / HDD tiered storage can be replaced by an all-QLC object tier.

Solidigm claims better energy efficiency compared to the competitors' Gen 5 drives from last year for various AI workload traces. While the data ingest and archival processes require system designers to maximize the storage capacity per watt (the QLC-based Solidigm D5-P5336 is attractive here), the core processing steps require the optimization of performance per watt. The D7-PS10x0 have a natural fit in this segment.

Solidigm / Intel has been serving the datacenter SSD market since its inception. The company is well aware of the quality and reliability requirements in this space. The D7-PS1010 and D7-PS1030 include the usual enhanced PLI (power loss imminent) validation checks for data saved in the process of power loss / restoration. The critical SRAMs in the SSD controller also have ECC protection. UBER testing goes well beyond the suggested JEDEC specifications. The company also claims that its silent data corruption testing and modeling are better than its competitors.

The new D7-PS1010 and D7-PS1030 bring class-leading Gen 5 performance to the datacenter SSD market. They are available for purchase now in both U.2 and E3.S form factors, with capacities ranging from 1.6 TB - 12.8 TB (D7-PS1030) and 1.92 TB - 15.36 TB (D7-PS1010).

Following Intel’s painful Q2 earnings call and the announcement of their 2025 cost reduction plan last week, it has become increasingly evident that Intel’s future is in the hands of their foundry group. Between Intel’s IDM 2.0 initiative and their internal chip production plans, all roads lead back to Intel retaking – and retaining – fab process leadership. To win as both a chip designer and a contract chip maker, Intel needs to be able to regain the fab technology lead it once held. In many respects it’s a return to Intel’s classic (and most successful) operating model, but never has it been so risky at it is for the already weakened Intel.

Intel’s do-or-die dash for process leadership means that, for the next 18 months or so, all eyes are on the company’s 20A and 18A process nodes. The final nodes in their ambitious 5 Nodes in 4 Years roadmap, the twinned 20A/18A are the culmination of several new technologies, primarily Intel’s GAAFET implementation (RibbonFET), which is being combined with PowerVia, Intel’s backside power delivery network (BS-PDN) technology. 20A is set to serve as Intel’s early version of the node, and 18A the refined version for long-term use both internally, and as the first major external node for Intel Foundry. To say that everything rides on Intel 18A isn’t quite accurate, but it’s only a slight embellishment.

To that end, we’re going to see Intel deliver a lot of status updates on 18A over the next year as they continue to outline to investors and external customers alike that they have the manufacturing side of their business in order. And today is one of those days, with a fresh update on the state of 18A.

18A Chips Back & Booting

So what’s new with 18A? The biggest news out of Intel this morning is that their first 18A chips are back from the development fab and are successfully booting operating systems. This means the silicon not only works (power-on), but works well enough to complete core tasks. It’s a major step in bringing up a chip, and at this point, Intel wants to make sure to let the whole world know.

Earlier this year the company finished taping out both of its lead 18A chips: Panther Lake for clients, and Clearwater Forest for servers. And it’s both chips that are booting. This is made all the more significant by the fact that Clearwater Forest also relies on Intel’s die-to-die hybrid bonding packaging technology, Foveros Direct 3D, where it will be the lead product for that technology as well. Which for Intel, is a promising sign that not only are their silicon lithography ambitions paying off, but their intention to lead in advanced packaging is on-track as well.

And while Intel doesn’t normally talk about yields this early in the game, it’s interesting to note that in a separate Q&A being published this morning with Intel Foundry’s new boss, Kevin O’Buckley, the head of Foundry Services explicitly comments that Panther Lake is “yielding well”. Similarly, Panther Lake’s DDR memory controller (a complex block mixing logic with a PHY) is already running at its target frequency. Progress is going so well, apparently, that according to O’Buckley, it’s ahead of schedule on its product qualification milestones.

PDK 1.0 Released, First External Customer Tape-Out Expected in H1’25

As for Intel’s contract foundry business, the company is ramping up its efforts there now that the first full process design kit (PDK) is ready for 18A. Intel released their 18A PDK 1.0 last month, giving Intel’s customers (and potential customers) the tools to finally finish designing their chips for production. As is typically the case of a new node, pre-release PDKs were available for companies to get started on their designs, but the 1.0 PDK is typically needed to finish those designs and align them with the formal and finalized process specifications.

For Intel, getting an external PDK out for a leading-edge process node is no small feat, as the company has spent decades operating its fabs for the benefit of its internal product design teams. A useful PDK for external customers – and really, a useful fab environment altogether – not only needs process nodes that stick to their specifications rather than making bespoke adjustments, but it means that Intel needs to document and define all of this in a useful, industry standard fashion. One of the major failings of Intel’s previous efforts to get into the contract foundry business, besides being half-hearted efforts overall, is that they didn’t author PDKs that external companies could easily use. At the end of the day, Intel is looking to woo customers from TSMC and Samsung, and as such Intel needs to provide PDKs that chip designers accustomed to contemporary contract fabs can use.

Those efforts are finally paying off, if slowly. While still not sharing any names, Intel expects their first external customer chip design will tape out in the first half of 2025 (H1’25). And, as Intel hopes, it will be the first of many.

Ultimately, the hard work for Intel foundry is not yet complete, and it will continue from here. With initial 18A development wrapping up, Intel’s needs are no longer just fab R&D, but marketing and customer relations. Which, going back to the start of this article, is why Intel is so keen to release status updates on 18A: it’s part of a broader approach to entice new customers to give Intel a try. Even in the best-case scenario, it will take upwards of a decade to capture a majority of the market for fabbing cutting-edge chips. But Intel has to start that marketing push if they’re going to get there.

In the meantime, if all continues going well for Intel, we should be seeing the first 18A chips released in the latter half of near year.

Last month, AMD launched their first processors using the Zen 5 microarchitecture for the mobile market via their Ryzen AI 300 series. Typically, with AMD Ryzen launches, we usually see the desktop parts come first, with the flagship model and then the mobile coming after. This time around, AMD has changed the dynamic of their release schedule with Zen 5 by launching the mobile chips first, which includes the Ryen AI 9 HX 370, which we reviewed last month. Today, Zen 5 on desktop has its turn, as AMD has launched two mid-range desktop processors, the Ryzen 7 9700X and the Ryzen 5 9600X.

AMD has launched two of the four announced Ryzen 9000 series processors today. The entry-level model is the Ryzen 5 9600X, a 6C/12T part with full-sized Zen 5 cores that can boost up to 5.4 GHz out of the box. The other model launched today is the Ryzen 7 9700X, which also features 8C/16T of Zen 5 and a boost clock speed of up to 5.5 GHz.

As part of AMD's push on platform longevity, the Ryzen 9000 series shares the same AM5 socket as its predecessor, meaning users can use X670E/X670 and B650E/B650 motherboards with a firmware update. We expected to see the newer X870X motherboards come with the Ryzen 9000 release, but unfortunately, these have been delayed.

So now we have Zen 5 in the form of the Ryzen 9000 series finally hitting the desktop, sans the top two SKUs, the Ryzen 9 9950X and Ryzen 9 9900X, which are coming later, it's time to see how much of an improvement Zen 5 is over Zen 4, not just in single-threaded but also multi-threaded workloads as AMD has promised up to an uplift of16% IPC on average. Both the Ryzen 7 9700X and Ryzen 5 9600X have a TDP of 65 W, which we see as more aligned with the non-X SKUs, so it will be interesting to see how Zen 5 performs in terms of both performance and efficiency.

A week after Western Digital confirmed that it had begun sampling of its 64 TB SSDs for datacenters, the company has teased its next-generation product, a 128 TB solid-state drive at FMS 2024.

For now, all we know about Western Digital's 128 TB SSD is that it uses the company's BiCS8 QLC NAND memory and is designed primarily for 'fast AI data lakes and capacity-intensive performance applications,' as Western Digital does not seem to be disclosing too much information about its upcoming product. The sample on the show floor indicates the usage of a U.2/U.3 form-factor suitable for GPU servers.

BiCS8 NAND has 218 layers and uses a hybrid bonding scheme that is being tagged as CMOS directly bonded to Array (CBA). It must be noted that this technique is an evolutionary successor to Micron's CMOS-under-Array (CuA) and SK hynix's Periphery-under-Cell (4D PUC) technologies. BiCS8 NAND can interface to the controller at rates of up to 3600 MT/s, making it suitable for Gen 4+ drives.

The technology demonstration on the show floor had the drive's firmware optimized for AI checkpointing - a workload that involves sequential writes, but also requires the drive to support a minimum QoS for simultaneous read operations.

Western Digital is not the only company to talk about high-performance 128 TB SSDs. Samsung recently said that it has technology to build 120 TB-class drives, and Solidigm was also demonstrating a proof-of-concept 122 TB QLC SSD at FMS 2024. AI workloads have triggered an insatiable need for dense and power-efficient storage in the data center. This has served as an impetus for enterprise SSD vendors to continue pushing the envelop on the per-drive capacity front.

AMD has made itself quite a reputation with its bundling campaigns over the years, and every new season we can be sure that the company will be giving away free games with the purchase of its hardware. This summer will certainly not be exception as AMD will be bundling Warhammer 40,000: Space Marine 2 and Unknown 9: Awakening titles with its Ryzen 7000 CPUs and Radeon RX 7000 video cards.

The latest bundle offer essentially covers all of AMD's existing mid-range and high-end consumer desktop products, sans the to-be-launched Ryzen 9000 series. That includes not only AMD's desktop parts, such as the Ryzen 9 7800X3D, but also virtually their entire stack of Radeon RX 7000 video cards, right on down to the 7600 XT.

AMD's laptop hardware is also covered as well, which is a much rarer occurence. Mid-range and high-end Ryzen 7000 mobile parts are part of the game bundle, including the 7940HS and even the 7435HS. However the refreshed version of these parts, sold under the Ryzen 8000 Mobile line, are not. Meanwhile systems with a Radeon RX 7700S or 7600S mobile GPU are included as well.

This deal is available only through participating retailers (in case of the U.S. and Canada these are Amazon and Newegg). The promotion is also applicable to select laptops containing these components. 

Warhammer 40,000: Space Marine 2 carries an MSRP of $60, whereas the Unknown 9: Awakening is set at $50, so this offer provides an estimated value of $110. The deal is particularly appealing to gamers and those interested in action titles. Meanwhile, fans of such games probably already have AMD's Ryzen 7000 and Radeon RX 7000-series products, so while the deal will be appealing to some users, it may not be appealing for gamers looking to upgrade to AMD's latest Zen 5-powered CPUs.

The campaign starts on August 6, 2024, at 9:00 AM ET and ends on October 5, 2024, at 11:59 PM ET, or when all Coupon Codes are claimed, whichever happens first. Coupon Codes must be redeemed by November 2, 2024, at 11:59 PM ET. 

Corsair, a prominent figure in PC components, has announced a strategic shift in its approach to power supply unit (PSU) certifications. The company is dropping the widely recognized 80 PLUS certification in favor of the newer but more comprehensive Cybenetics certification.

According to the press release, the primary reason for Corsair’s move to Cybenetics certifications lies in the program's dual focus on both energy efficiency and noise levels. While the 80 PLUS certification has been a standard in the industry for decades, it exclusively measures energy conversion efficiency at four load levels (10%, 20%, 50%, 100%). Despite its long-standing presence, the 80 PLUS program has not seen significant updates in over 15 years, which limits its ability to provide a holistic view of PSU performance.

On the other hand, Cybenetics offers a more nuanced approach. It evaluates PSUs across multiple load levels and includes noise level assessments. This dual certification system rates efficiency on a familiar scale (Bronze to Titanium, plus a higher certification called Diamond) and noise levels from Standard (noisy) to A++ (virtually silent). By incorporating noise measurements, Cybenetics provides a more comprehensive overview of PSU performance, addressing an important aspect often overlooked by other certification programs. Cybenetics also enforces Power Factor, 5VSB efficiency, and Vampire Power thresholds, all important to the overall efficiency of a PSU.

Even though they're dropping 80 PLUS in favor of Cybernetics, Corsair is being highly diplomatic with their press release. They even suggest that the reader should not disregard either in favor of the other.

Our opinion is a bit harsher: the simplicity of the 80 PLUS certification program has led to two major flaws. First, manufacturers have primarily focused on maximizing efficiency at three specific load points, neglecting overall performance. Second, the majority of PSUs have clustered around the 80 PLUS Gold and Platinum certifications, with very few achieving the stringent Titanium level. This results in hundreds of PSUs with significantly different technical capabilities sharing the same certification badge, creating a misleading uniformity that fails to reflect true performance disparities.

Furthermore, almost every PSU platform that has been released over the past 15 years would achieve 80Plus Gold status or greater, with very few products falling down to the 80Plus Bronze certification and almost zero meeting the 80Plus White and 80Plus Silver requirements, making the three lowermost certifications practically defunct. Cybenetics dual certification certainly does not solve every issue and cannot fully assess everything there is to assess about a PSU, but it certainly makes much more information available to the user and allows users to at least factor in acoustics performance when purchasing a product.

The issue that seems to remain is that, due to the slackest requirements, manufacturers were almost always certifying their units with an input voltage of 115 VAC, resulting in myriads of units carrying a certification badge that would fail the same 80Plus certification requirements with an input voltage of 230 VAC. Unfortunately, this is also true for the Cybenetics standard, as the badges do not inform the user about the input voltage that the certification was attained with. However, as the Cybenetics standard revolves around average efficiency and not efficiency at specific load points, the majority of the PSUs should meet both efficiency thresholds and not the other way around.

Certification processes can be costly for manufacturers. By opting for the Cybenetics program, Corsair possibly aims to get the most value from its certification investments. Cybenetics offers more detailed and up-to-date testing methodologies, ensuring that the data provided is more reflective of real-world usage scenarios. In any case, Corsair’s shift to Cybenetics certification marks a significant development in the evaluation of PSUs and has the potential to create waves in the market.

Ultimately, this move has the potential disrupt the status quo. With Corsair's sheer size and influence in the larger power supply market, this could very well prompt other manufacturers to follow suit, and possibly even reshape consumer expectations and benchmarks for PSU quality.

Solidigm's D5-P5336 61.44 TB enterprise QLC SSD released in mid-2023 has seen unprecedented demand over the last few quarters, driven by the insatiable demand for high-capacity storage in AI datacenters. Multiple vendors have recognized and started preparing products to service this demand, but Solidigm appears to have taken the lead in actual market availability.

At FMS 2024, Solidigm previewed a U.2 version of their upcoming 122 TB enterprise QLC SSD. The proof-of-concept Gen 4 drives were running live in a 2U server, and Solidigm is preparing them for an early 2025 release.

Given the capacity play, Solidigm will be relying on QLC technology. However, the company was coy about confirming the NAND generation used in the product.

Source: The Advantages of Floating Gate Technology (YouTube)

The 61.44 TB D5-P5336 currently utilizes Solidigm's 192L 3D QLC based on the floating gate architecture. This has a distinct advantage for QLC endurance compared to the charge trap architecture also available to Solidigm from SK hynix. That said, SK hynix's 238L NAND also has a QLC avatar, which gives Solidigm the flexibility to use either NAND for the production version of the 122 TB drive. Solidigm expects to confirm this by the end of year in preparation for volume shipment in the first half of 2025.

Silicon Motion has been teasing their SM2508 client SSD controller for more than a year now at various trade shows. The controller is finally set for mass production, just in time as the mainstream segment of the Gen 5 SSD market is poised to take off. Silicon Motion expects SSDs based on the SM2508 to be available for purchase by the end of the year.

At FMS 2024, the company was reusing the same information cards seen at Computex in June. The specifications of the SM2508 from our Computex coverage are reproduced here.

Current Gen 5 SSDs in the consumer client market are currently all based on Phison's E26 controller. The appearance of newer platform solutions for SSD vendors is bound to be good from both an end-user pricing and adoption perspective.

Silicon Motion's SM2320 native USB 3.2 Gen 2x2 controller for USB flash drives and portable SSDs has enjoyed great market success with a large number of design wins over the last few years. Silicon Motion proudly displayed a selection of products based on the SM2320 on the show floor at FMS 2024.

The SM2320 went into mass production in Q3 2021. Since then, the NAND flash market has seen considerable change. QLC is becoming more and more reliable and common, leading to the launch of high-capacity cost-effective 4 TB and 8 TB SSDs. Newer NAND generations with flash operating at higher speeds have also made an appearance.

The SM2320, fabricated in TSMC's 28nm node, supported four channels of NAND flash running at up to 800 MT/s. The new SM2322 uses the same process node and retains support for the same number of flash channels and chip enables (8 CEs per channel). However, the NAND can now operate at up to 1200 MT/s.

The SM2322 also improves the QLC support, thanks to the implementation of a better ECC scheme. While the SM2320 opted for a 2KB LDPC implementation, the SM2322 goes in for a 4KB LDPC solution. The use of a larger region enables extension of the NAND's useful life.

The SM2322 and SM2320 packages are similar in size, and Silicon Motion expects PSSD designs using the SM2320 to adopt the SM2322 with different NAND (higher capacity / speeds) using the same enclosure. Products based on the SM2322 are expected to appear in the market before the end of the year.

Imec and ASML have announced that the two companies have printed the first logic and DRAM patterns using ASML's experimental Twinscan EXE:5000 EUV lithography tool, the industry's first High-NA EUV scanner. The lithography system achieved resolution that is good enough for 1.4nm-class process technology with just one exposure, which confirms the capabilities of the system and that development of the High-NA ecosystem remains on-track for use in commercial chip production later this decade.

"The results confirm the long-predicted resolution capability of High NA EUV lithography, targeting sub 20nm pitch metal layers in one single exposure," said Luc Van den hove, president and CEO of imec. "High NA EUV will therefore be highly instrumental to continue the dimensional scaling of logic and memory technologies, one of the key pillars to push the roadmaps deep into the ‘angstrom era'. These early demonstrations were only possible thanks to the set-up of the joint ASML-imec lab allowing our partners to accelerate the introduction of High NA lithography into manufacturing."

The successful test printing comes after ASML and Imec have spent the last several months laying the groundwork for the test. Besides the years required to build the complex scanner itself, engineers from ASML, Imec, and their partners needed to develop newer photoresists, underlayers, and reticles. Then they had to take an existing production node and tune it for High-NA EUV tools, including doing optical proximity correction (OPC) and tuning etching processes.

The culmination of these efforts was that, using ASML's pre-production Twinscan EXE:5000 system, Imec was able to successfully pattern random logic structures with 9.5nm dense metal lines, which corresponds to a 19nm pitch and sub-20nm tip-to-tip dimensions. Similarly, Imec also set new high marks in feature density in other respects, including patterning of 2D features at a 22nm pitch, and printing random vias with a 30nm center-to-center distance, demonstrating high pattern fidelity and critical dimension uniformity.

The overall result is that Imec's experiments have proven that ASML's High-NA scanner is delivering on its intended capabilities, printing features at a fine enough resolution for fabricating logic on a 1.4nm-class process technology – and all with a single exposure. The latter is perhaps the most important aspect of this tooling, as the high cost and complexity of the High-NA tool itself (said to be around $400 million) is intended to be offset by being able to return to single-patterning, which allows for higher tool productivity and fewer steps overall.

Imec hasn't just been printing logic structures, either; the group successfully patterned DRAM designs as well, printing both a storage node landing pad alongside the bit line periphery for memory in a single exposure. As with their logic tests, this would allow DRAM designs to be printed in just one exposure, reducing cycle times and eventually costs.

9,5nm random logic structure (19nm pitch) after pattern transfer

Gallery: imec High-NA Pattern Samples

"We are thrilled to demonstrate the world's first High NA-enabled logic and memory patterning in the joint ASML-imec lab as an initial validation of industry applications," said Steven Scheer, senior vice president of compute technologies & systems/compute system scaling at imec. "The results showcase the unique potential for High NA EUV to enable single-print imaging of aggressively-scaled 2D features, improving design flexibility as well as reducing patterning cost and complexity. Looking ahead, we expect to provide valuable insights to our patterning ecosystem partners, supporting them in further maturing High NA EUV specific materials and equipment."