At MWC 2024, Intel confirmed that Granite Rapids-D, the successor to Ice Lake-D processors, will come to market sometime in 2025. Furthermore, Intel also provided an update on the 6th Gen Xeon Family, codenamed Sierra Forest, which is set to launch later this year and will feature up to 288 cores designed for vRAN network operators to improve performance in boost per rack for 5G workloads.

These chips are designed for handling infrastructure, applications, and AI workloads and aim to capitalize on current and future AI and automation opportunities, enhancing operational efficiency and ownership costs in next-gen applications and reflecting Intel's vision of integrating 'AI Everywhere' across various infrastructures.

Intel Sierra Forest: Up to 288 Efficiency Cores, Set for 2H 2024

The first of Intel's announcements at MWC 2024 focuses on their upcoming Sierra Forest platform, which is scheduled for the 1st half of 2024. Initially announced in February 2022 during Intel's Investor Meeting, Intel is splitting its server roadmap into solutions featuring only performance (P) and efficiency (E) cores. We already know that Sierra Forest's new chips feature a full E-core architecture designed for maximum efficiency in scale-out, cloud-native, and contained environments.

These chips utilize CPU chiplets built on the Intel 3 process alongside twin I/O chiplets based on the Intel 7 node. This combination allows for a scalable architecture, which can accommodate increasing core counts by adding more chiplets, optimizing performance for complex computing environments.

Intel's Sierra Forest, Intel's full E-core designed Xeon processor family, is anticipated to significantly enhance power efficiency with up to 288 E-cores per socket. Intel also claims that Sierra Forest is expected to deliver 2.7 times the performance-per-rack compared to an unspecified platform from 2021; this could be either Ice Lake or Cascade Lake, but Intel didn't mention which.

Additionally, Intel is promising savings of up to 30% in Infrastructure Power Management with Sierra Forest as their Infrastructure Power Manager (IPM) application is now available commercially for 5G cores. Power manageability and efficiency are growing challenges for network operators, so IPM is designed to allow network operators to optimize energy efficiency and TCO savings.

Intel also includes vRAN, which is vital for modern mobile networks, and many operators are forgoing opting for specific hardware and instead leaning towards virtualized radio access networks (vRANs). Using vRAN Boost, which is an integrated accelerator within Xeon Processors, Intel states that the 4th Gen Xeon should be able to reduce power consumption by around 20% while doubling the available network capacity.

Intel's push for 'AI Everywhere' is also a constant focus here, with AI's role in vRAN management becoming more crucial. Intel has announced the vRAN AI Developer Kit, which is available to select partners. This allows partners and 5G network providers to develop AI models to optimize for vRAN applications, tailor their vRAN-based functions to more use cases, and adapt to changes within those scenarios.

Intel Granite Rapids-D: Coming in 2025 For Edge Solutions

Intel's Granite Rapids-D, designed for Edge solutions, is set to bolster Intel's role in virtual radio access network (vRAN) workloads in 2025. Intel also promises marked efficiency enhancements and some vRAN Boost optimizations similar to those expected on Sierra Forest. Set to follow on from the current Ice Lake-D for the edge; Intel is expected to use the performance (P) cores used within Granite Rapids server parts and optimize the V/F curve designed for the lower-powered Edge platform. As outlined by Intel, the previous 4th generation Xeon platform effectively doubled vRAN capacity, enhancing network capabilities while reducing power consumption by up to 20%.

Granite Rapids-D aims to further these advancements, utilizing Intel AVX for vRAN and integrated Intel vRAN Boost acceleration, thereby offering substantial cost and performance benefits on a global scale. While Intel hasn't provided a specific date (or month) of when we can expect to see Granite Rapids-D in 2025, Intel is currently in the process of sampling these next-gen Xeon-D processors with partners, aiming to ensure a market-ready platform at launch.

Gallery: Intel Sierra Forest and Granite Rapids-D Slide Deck MWC 2024

Related Reading

• Hot Chips 2023: Intel Details More on Granite Rapids and Sierra Forest Xeons
• Intel Updates Data Center Roadmap: Xeons on Track - Emerald in Q4'23, Sierra Forest in H1'24
• IFS Reborn as Intel Foundry: Expanded Foundry Business Adds 14A Process to Roadmap

Micron Technology on Monday said that it had initiated volume production of its HBM3E memory. The company's HBM3E known good stack dies (KGSDs) will be used for Nvidia's H200 compute GPU for artificial intelligence (AI) and high-performance computing (HPC) applications, which will ship in the second quarter of 2024.

Micron has announced it is mass-producing 24 GB 8-Hi HBM3E devices with a data transfer rate of 9.2 GT/s and a peak memory bandwidth of over 1.2 TB/s per device. Compared to HBM3, HBM3E increases data transfer rate and peak memory bandwidth by a whopping 44%, which is particularly important for bandwidth-hungry processors like Nvidia's H200.

Nvidia's H200 product relies on the Hopper architecture and offers the same computing performance as the H100. Meanwhile, it is equipped with 141 GB of HBM3E memory featuring bandwidth of up to 4.8 TB/s, a significant upgrade from 80 GB of HBM3 and up to 3.35 TB/s bandwidth in the case of the H100.

Micron's memory roadmap for AI is further solidified with the upcoming release of a 36 GB 12-Hi HBM3E product in March 2024. Meanwhile, it remains to be seen where those devices will be used.

Micron uses its 1β (1-beta) process technology to produce its HBM3E, which is a significant achievement for the company as it uses its latest production node for its data center-grade products, which is a testament to the manufacturing technology.

Starting mass production of HBM3E memory ahead of competitors SK Hynix and Samsung is a significant achievement for Micron, which currently holds a 10% market share in the HBM sector. This move is crucial for the company, as it allows Micron to introduce a premium product earlier than its rivals, potentially increasing its revenue and profit margins while gaining a larger market share.

"Micron is delivering a trifecta with this HBM3E milestone: time-to-market leadership, best-in-class industry performance, and a differentiated power efficiency profile," said Sumit Sadana, executive vice president and chief business officer at Micron Technology. "AI workloads are heavily reliant on memory bandwidth and capacity, and Micron is very well-positioned to support the significant AI growth ahead through our industry-leading HBM3E and HBM4 roadmap, as well as our full portfolio of DRAM and NAND solutions for AI applications."

Source: Micron

Samsung announced late on Monday the completion of the development of its 12-Hi 36 GB HBM3E memory stacks, just hours after Micron said it had kicked off mass production of its 8-Hi 24 GB HBM3E memory products. The new memory packages, codenamed Shinebolt, increase peak bandwidth and capacity compared to their predecessors, codenamed Icebolt, by over 50% and are currently the world's fastest memory devices.

As the description suggests, Samsung's Shinebolt 12-Hi 36 GB HBM3E stacks pack 12 24Gb memory devices on top of a logic die featuring a 1024-bit interface. The new 36 GB HBM3E memory modules feature a data transfer rate of 10 GT/s and thus offer a peak bandwidth of 1.28 TB/s per stack, the industry's highest per-device (or rather per-module) memory bandwidth.

Meanwhile, keep in mind that developers of HBM-supporting processors tend to be cautious, so they will use Samsung's HBM3E at much lower data transfer rates to some degree because of power consumption and to some degree to ensure ultimate stability for artificial intelligence (AI) and high-performance computing (HPC) applications.

To make its Shinebolt 12-Hi 36 GB HBM3E memory stacks, Samsung had to use several advanced technologies. First, the 36 GB HBM3E memory products are based on memory devices made on Samsung's 4^th generation 10nm-class (14nm) fabrication technology, which is called and uses extreme ultraviolet (EUV) lithography.

Secondly, to ensure that 12-Hi HBM3E stacks have the same z-height as 8-Hi HBM3 products, Samsung used its advanced thermal compression non-conductive film (TC NCF), which allowed it to achieve the industry's smallest gap between memory devices at seven micrometers (7 µm). By shrinking gaps between DRAMs, Samsung increases vertical density and mitigates chip die warping. Furthermore, Samsung uses bumps of various sizes between the DRAM ICs; smaller bumps are used in areas for signaling. In contrast, larger ones are placed in spots that require heat dissipation, which improves thermal management.

Samsung estimates that its 12-Hi HBM3E 36 GB modules can increase the average speed for AI training by 34% and expand the number of simultaneous users of inference services by more than 11.5 times. However, the company has not elaborated on the size of the LLM.

Samsung has already begun providing samples of the HBM3E 12H to customers, with mass production scheduled to commence in the first half of this year.

Source: Samsung

As part of this week's MWC 2024 conference, Intel is announcing that it is adding support for its vPro security technologies to select 14th Generation Core series processors (Raptor Lake-R) and their latest Meteor Lake-based Core Ultra-H and U series mobile processors. As we've seen from more launches than we care to count of Intel's desktop and mobile platforms, they typically roll out their vPro platforms sometime after they've released their full stack of processors, including overclockable K series SKUs and lower-powered T series SKUs, and this year is no exception. Altogether, Intel is announcing vPro Essential and vPro Enterprise support for several 14th Gen Core series SKUs and Intel Core Ultra mobile SKUs.

Intel's vPro security features is something we've covered previously – and on that note, Intel has a new Silicon Security Engine giving the chips the ability to authentical the systems firmware. Intel also states that Intel Threat Detection within vPro has been enhanced and adds an additional layer for the NPU, with an xPU model (CPU/GPU/NPU) to help detect a variety of attacks, and also enables 3rd party software to fun faster. Intel claims is the only AI-based security deployment within a Windows PC to date. Both the total Enterprise securities and the cut-down Essentials vPro hardware-level security to select 14th Gen Core series processors, as well as their latest mobile-focused Meteor Lake processors with Arc graphics launched last year.

Intel 14th Gen vPro: Raptor Lake-R Gets Secured

As we've seen over the last few years with a global shift towards remote work due to the Coronavirus pandemic, the need for up-to-date security in small and larger enterprises is just as critical as it has ever been. Remote and employees in offices alike must have access to the latest software and hardware frameworks to ensure the security of vital data, and that's where Intel vPro comes in.

To quickly recap the current state of affairs, let's take a look at the two levels of Intel vPro securities available,  vPro Essentials and vPro Enterprise, and how they differ.

Intel's vPro Essentials was first launched back in 2022 and is a subset of Intel's complete vPro package, which is now commonly known as vPro Enterprise. The Intel vPro Essentials security package is essentially (as per the name) tailored and designed for small businesses, providing a solid foundation in security without penalizing performance. It integrates hardware-enhanced security features, ensuring hardware-level protection against emerging threats from right from its installation. It also utilizes real-time intelligence for workload optimization and Intel's Thread Detection Technology. It adds an additional layer below the operating system that uses AI-based threat detection to mitigate OS-level threats and attacks.

Pivoting to Intel vPro Enterprise security features, this is designed for SMEs to meet the high demands of large-scale business environments. It offers advanced security features and remote management capabilities, which are crucial for businesses operating with sensitive data and requiring high levels of cybersecurity. Additionally, the platform provides enhanced performance and reliability, making it suitable for intensive workloads and multitasking in a professional setting. Integrating these features from the vPro Enterprise platform ensures that large enterprises can maintain high productivity levels while ensuring data security and efficient IT management with the latest generations of processors, such as the Intel Core 14th Gen family.

Much like we saw when Intel announced their vPro for the 13th Gen Core series, it's worth noting that both the 14th and 13th Gen Core series are based on the same Raptor Lake architecture and, as such, are identical in every aspect bar base and turbo core frequencies.

While Intel isn't technically launching any new chip SKUs (either desktop or mobile) with vPro support, the vPro desktop platform features are enabled through the use of specific motherboard chipsets, with both Q670 and W680 chipsets offering sole support for vPro on 14th Gen. Unless users are using either a Q670 or W680 motherboard with the specific chips listed above. vPro Essentials or Enterprise will not be enabled or work with each processor unless installed into a motherboard from one of these chipsets.

As with the previous 13th Gen Core series family (Raptor Lake), the 14th Gen, which is a direct refresh of these, follows a similar pattern. Specific SKUs from the 14th Gen family include support only for the full-fledged vPro Enterprise, including the Core i5-14600K, the Core i7-14700K, and the flagship Core i9-14900K. Intel's vPro Enterprise security features are supported on both Q670 and W680 motherboards, giving users more choice in which board they opt for.

The rest of the above Intel 14th Gen Core series stack, including the non-monikered chips, e.g., the Core i5-14600, as well as the T series, which are optimized for efficient workloads with a lower TDP than the rest of the stack, all support both vPro Enterprise and vPro Essentials. This includes two processors from the Core i9 family, including the Core i9-14900 and Core i9-14900T, two from the i7 series, the Core i7-14700 and Core i7-14700T, and four from the i5 series, the Core i5-14600, Core i5-14500, the Core i5-14600T and the COre i5-14500T.

The ASRock Industrial IMB-X1231 W680 mini-ITX motherboard supports vPro Enterprise and Essentials

For the processors mentioned above (non-K), different levels of vPro support are offered depending on the motherboard chipset. If a user wishes to use a Q670 motherboard, then users can specifically opt to use Intel's cut-down vPro Essentials security features. Intel states that users with a Q670 or W680 can use the full vPro Enterprise security features, including the Core i9-14900K, the Core i7-14700K, and the Core i5-14600K. Outside of this, none of the 14th Gen SKUs with the KF (unlocked with no iGPU) and F (no iGPU) monikers are listed with support for vPro.

Intel Meteor Lake with vPro: Core Ultra H and U Series get Varied vPro Support

Further to the Intel 14th Gen Core series for desktops, Intel has also enabled vPro support for their latest Meteor Lake-based Core Ultra H and U series mobile processors. Unlike the desktop platform for vPro, things are a little different in the mobile space, as Intel offers vPro on their mobile SKUs, either with vPro Enterprise or vPro Essentials, not both.

The above table highlights not just the specifications of each Core Ultra 9, 7, and 5 SKU but also denotes which model gets what level of vPro support. Starting with the Core Ultra 9 185H processor, the current mobile flagship chip on Meteor Lake, this chip supports vPro Enterprise. Along with the other top-tier SKU from each of the Core Ultra 9, 7, and 5 families, including the Core Ultra 7 165H and the Core Ultra 135H, other chips with vPro Enterprise support include the Core Ultra 7 165U and Core Ultra 7 164U, as well as the Core Ultra 5 135U and Core Ultra 5 134U.

Intel's other Meteor Lake chips, including the Core Ultra 7 155H, the Core Ultra 7 155U, the Core Ultra 5 125H, and the Core Ultra 5 125U, only come with support Intel's vPro Essentials features and not with support for Enterprise This presents a slight 'dropping of the ball' from Intel on this, which we highlighted in our Intel 13th Gen Core gets vPro piece last year.

Intel vPro Support Announcement With No New Hardware, Why Announce Later?

It is worth noting that Intel's announcement of adding vPro support to their first launch of Meteor Lake Core Ultra SKUs isn't entirely new; Intel did highlight that Meteor Lake would support vPro last year within their Series 1 Product Brief dated 12/20/2023. Intel's formal announcement of vPro support for Meteor Lake is more about which SKU has which level of support, and we feel this could pose problems to users who have already purchased Core Ultra series notebooks for business and enterprise use. Multiple outlets, including Newegg and directly from HP, are alluding to mentioning vPro whatsoever.

This could mean that a user has purchased a notebook with, say, a Core Ultra 5 125H (vPro Essentials), which would be used within an SME or by said SME as a bulk purchase but wouldn't be aware that the chip doesn't have vPro Enterprise, from which they personally and from a business standpoint could benefit from the additional securities. We reached out to Intel, and they sent us the following statement.

"Since we are launching vPro powered by Intel Core Ultra & Intel Core 14th Gen this week, prospective buyers will begin seeing the relevant system information on OEM and enterprise retail partner (eg. CDW) websites in the weeks ahead. This will include information on whether a system is equipped with vPro Enterprise or Essentials so that they can purchase the right system for their compute needs."

Gallery: Intel vPro Security Slide Deck

Tenstorrent this week announced that it had signed a deal to license out its RISC-V CPU and AI processor IP to Japan's Leading-edge Semiconductor Technology Center (LSTC), which will use the technology to build its edge-focused AI accelerator. The most curious part of the announcement is that this accelerator will rely on a multi-chiplet design and the chiplets will be made by Japan's Rapidus on its 2nm fabrication process, and then will be packaged by the same company.

Under the terms of the agreement, Tenstorrent will license its datacenter-grade Ascalon general-purpose processor IP to LSTC and will help to implement the chiplet using Rapidus's 2nm fabrication process. Tenstorrent's Ascalon is a high-performance out-of-order RISC-V CPU design that features an eight-wide decoding. The Ascalon core packs six ALUs, two FPUs, and two 256-bit vector units and when combined with a 2nm-class process technology promises to offer quite formidable performance.

The Ascalon was developed by a team led by legendary CPU designer Jim Keller, the current chief executive of Tenstorrent, who used to work on successful projects by AMD, Apple, Intel, and Tesla.

In addition to general-purpose CPU IP licensing, Tenstorrent will co-design 'the chip that will redefine AI performance in Japan.' This apparently means that Tenstorrent  does not plan to license LSTC its proprietary  Tensix cores tailored for neural network inference and training, but will help to design a proprietary AI accelerator generally for inference workloads.

"The joint effort by Tenstorrent and LSTC to create a chiplet-based edge AI accelerator represents a groundbreaking venture into the first cross-organizational chiplet development in semiconductor industry," said Wei-Han Lien, Chief Architect of Tenstorrent's RISC-V products. "The edge AI accelerator will incorporate LSTC's AI chiplet along with Tenstorrent's RISC-V and peripheral chiplet technology. This pioneering strategy harnesses the collective capabilities of both organizations to use the adaptable and efficient nature of chiplet technology to meet the increasing needs of AI applications at the edge."

Rapidus aims to start production of chips on its 2nm fabrication process that is currently under development sometimes in 2027, at least a year behind TSMC and a couple of years behind Intel. Yet, if it starts high-volume 2nm manufacturing in 2027, it will be a major breakthrough from Japan, which is trying hard to return to the global semiconductor leaders.

Building an edge AI accelerator based on Tenstorrent's IP and Rapidus's 2nm-class production node is a big deal for LSTC, Tenstorrent, and Rapidus as it is a testament for technologies developed by these three companies.

"I am very pleased that this collaboration started as an actual project from the MOC conclusion with Tenstorrent last November," said Atsuyoshi Koike, president and CEO of Rapidus Corporation. "We will cooperate not only in the front-end process but also in the chiplet (back-end process), and work on as a leading example of our business model that realizes everything from design to back-end process in a shorter period of time ever."

Cooler Master, renowned for its pioneering role in cooling technologies, has evolved into a key player in the PC components industry, extending its expertise to include cases and power supply units (PSUs). The company's current catalog is a testament to its commitment to diversity, featuring over 75 PC cases, 90 coolers, and 120 PSUs, all designed to cater to the evolving demands of tech enthusiasts and professionals alike.

This review focuses on the Cooler Master MWE Gold V2 750W PSU, a key offering in Cooler Master's power supply lineup that embodies the brand's vision of combining quality and value. The MWE Gold V2 series is engineered to offer solid performance and reliability at a price point that appeals to system builders and gamers looking for an entry-level to mid-range solution. As a result, the MWE Gold V2 750W has been a consistently popular offering within Cooler Master's catalog, often cycling in and out of stock depending on what sales are going on. This makes the PSU a bit harder to track down in North America than it does Europe, and quick to vanish when it does show up.

SK Hynix and AMD were at the forefront of the memory industry with the first generation of high bandwidth memory (HBM) back in 2013 – 2015, and SK Hynix is still leading this market in terms of share. In a bid to maintain and grow its position, SK Hynix has to adapt to the requirements of its customers, particularly in the AI space, and to do so it's mulling over how to make 'differentiated' HBM products for large customers.

"Developing customer-specific AI memory requires a new approach as the flexibility and scalability of the technology becomes critical," said Hoyoung Son, the head of Advanced Package Development at SK Hynix in the status of a vice president

When it comes to performance, HBM memory with a 1024-bit interface has been evolving fairly fast: it started with a data transfer rate of 1 GT/s in 2014 – 2015 and reached upwards of 9.2 GT/s – 10 GT/s with the recently introduced HBM3E memory devices. With HBM4, the memory is set to transit to a 2048-bit interface, which will ensure steady bandwidth improvement over HBM3E.

But there are customers which may benefit from differentiated (or semi-custom) HBM-based solutions, according to the vice president.

"For implementing diverse AI, the characteristics of AI memory also need to become more varied," Hoyoung Son said in an interview with BusinessKorea. "Our goal is to have a variety of advanced packaging technologies capable of responding to these changes. We plan to provide differentiated solutions that can meet any customer needs."

With a 2048-bit interface, many (if not the vast majority) of HBM4 solutions will likely be custom or at least semi-custom based on what we know from official and unofficial information about the upcoming standard. Some customers might want to keep using interposers (but this time they are going to get very expensive) and others will prefer to install HBM4 modules directly on logic dies using direct bonding techniques, which are also expensive.

Making differentiated HBM offerings requires sophisticated packaging techniques, including (but certainly not limited to) SK Hynix's Advanced Mass Reflow Molded Underfill (MR-RUF) technology. Given the company's vast experience with HBM, it may well come up with something else, especially for differentiated offerings.

"For different types of AI to be realized, the characteristics of AI memory also need to be more diverse," the VP said. "Our goal is to have a range of advanced packaging technologies to respond to the shifting technological landscape. Looking ahead, we plan to provide differentiated solutions to meet all customer needs."

Sources: BusinessKorea, SK Hynix

Silicon Power announced the MS70 and PX10 Portable SSDs in late 2023. The company is well known for offering entry- and mid-range products at compelling price points, but the two products came with plenty of promises in the 1GBps-class category. The MS70 promised high storage density (up to 2TB in a compact thumb drive), while the PX10 targeted power users and professionals with performance consistency as the focus. Read on for a detailed look at the Silicon Power PX10 including an analysis of its internals, value proposition, and evaluation of its performance consistency, power consumption, and thermal profile.

Apple on Monday introduced its new generation MacBook Air laptops based on the company's most-recent M3 system-on-chip (SoC). The new MacBook Air notebooks come in the same sizes as the previous models – 13.6 inches and 15.3 inches – with prices starting from $1,099 and $1,299 respectively.

The key improvement in Apple's 2024 MacBook Air laptops is of course the M3 processor. Fabbed on TSMC's N3B process, Apple's latest mainstream SoC was first launched late last year as part of the 2023 MacBook Pro lineup, and is now being brought down to the MacBook Air family. The vanilla M3 features four high-performance cores operating at up to 4.05 GHz, four energy-efficient cores, a 10 core GPU based on the latest graphics architecture (with dynamic caching, hardware-accelerated ray tracing, and hardware-accelerated mesh shading), and a new media engine with hardware-accelerated AV1 decoding.

Like prior vanilla M-series SoC, the M3 offers two display engines, allowing it to drive up to two displays. Normally this has been one internal and one external display, but new to the M3/2024 MBAs, the laptop can also drive two external 5K displays when the internal display is disabled (e.g. the lid's closed).

With regards to performance, Apple is opting to compare the new AIrs to the 2020 models with Apple's M1 SoC. The CPU is said to be up to 35% – 60% faster compared to the original M1 chip depending on the workload, but such comparisons should be taken with a grain of salt as companies tend to overhype their biggest advantages. One thing to keep in mind is that since MacBook Airs come without active cooling, their performance is typically lower than MacBook Pros running the same processor.

The SoC supports up to 24 GB of LPDDR5-6400 memory (featuring bandwidth of 100 GB/s), though entry-level MacBook Air models still feature only a diminutive 8 GB of RAM and a 256 GB SSD. More advanced (and usable) configurations offer 16 GB or 24 GB of memory and up to 2 TB of solid-state storage.

Other improvements of Apple's 2024 MacBook Air laptops based on the M3 processor compared to predecessors include Wi-Fi 6E support;  improved three-microphones array with enhanced voice clarity, voice isolation, and wide spectrum modes.

As for input/output capabilities, the new MacBook Air notebooks feature two Thunderbolt 4/USB-C ports, a MagSafe port for charging, a 3.5-mm jack for headsets, and a 1080p FaceTime HD camera.

The 2024 Apple MacBook Air come in midnight, starlight, silver, and space gray colors. The machines are equipped with a 52.6 Wh battery that provides up to 18 hours of video playback. The 13.6-inch machine is 0.44 inch (1.13 cm) thick and weighs 2.7 pounds (1.24 kilograms), whereas the 15.3-inch laptop is 0.45 inch (1.15 cm) thick and weighs 3.3 pounds (1.51 kilograms).

With the launch of its M3-based MacBook Airs, Apple will discontinue its M2-based MacBook Air 15, but will retain the M2-based MacBook Air 13 as their entry-level option, with prices now starting at $999.

JEDEC on Tuesday published the official specifications for GDDR7 DRAM, the latest iteration of the long-standing memory standard for graphics cards and other GPU-powered devices. The newest generation of GDDR brings a combination of memory capacity and memory bandwidth gains, with the later being driven primarily by the switch to PAM3 signaling on the memory bus. The latest graphics RAM standard also boosts the number of channels per DRAM chip, adds new interface training patterns, and brings in on-die ECC to maintain the effective reliability of the memory.

“JESD239 GDDR7 marks a substantial advancement in high-speed memory design,” said Mian Quddus, JEDEC Board of Directors Chairman. “With the shift to PAM3 signaling, the memory industry has a new path to extend the performance of GDDR devices and drive the ongoing evolution of graphics and various high-performance applications.”

GDDR7 has been in development for a few years now, with JEDEC members making the first disclosures around the memory technology about a year ago, when Cadence revealed the use of PAM3 encoding as part of their validation tools. Since then we've heard from multiple memory manufacturers that we should expect the final version of the memory to launch in 2024, with JEDEC's announcement essentially coming right on schedule.

As previously revealed, the biggest technical change with GDDR7 comes with the switch from two-bit non-return-to-zero (NRZ) encoding on the memory bus to three-bit pulse amplitude modulating (PAM3) encoding. This change allows GDDR7 to transmit 3 bits over two cycles, 50% more data than GDDR6 operating at an identical clockspeed. As a result, GDDR7 can support higher overall data transfer rates, the critical component to making each generation of GDDR successively faster than its predecessor.

The first generation of GDDR7 is expected to run at data rates around 32 Gbps per pin, and memory manufacturers have previously talked about rates up to 36 Gbps/pin as being easily attainable. However the GDDR7 standard itself leaves room for even higher data rates – up to 48 Gbps/pin – with JEDEC going so far as touting GDDR7 memory chips "reaching up to 192 GB/s [32b @ 48Gbps] per device" in their press release. Notably, this is a significantly higher increase in bandwidth than what PAM3 signaling brings on its own, which means there are multiple levels of enhancements within GDDR7's design.

Digging deeper into the specification, JEDEC has also once again subdivided a single 32-bit GDDR memory chip into a larger number of channels. Whereas GDDR6 offered two 16-bit channels, GDDR7 expands this to four 8-bit channels. The distinction is somewhat arbitrary from an end-user's point of view – it's still a 32-bit chip operating at 32Gbps/pin regardless – but it has a great deal of impact on how the chip works internally. Especially as JEDEC has kept the 256-bit per channel prefetch of GDDR5 and GDDR6, making GDDR7 a 32n prefetch design.

GDDR Channel Architecture. Original GDDR6-era Diagram Courtesy Micron

The net impact of all of this is that, by halving the channel width but keeping the prefetch size the same, JEDEC has effectively doubled the amount of data that is prefetched per cycle of the DRAM cells. This is a pretty standard trick to extend the bandwidth of DRAM memory, and is essentially the same thing JEDEC did with GDDR6 in 2018. But it serves as a reminder that DRAM cells are still very slow (on the order of hundreds of MHz) and aren't getting any faster. So the only way to feed faster memory buses is by fetching ever-larger amounts of data in a single go.

The change in the number of channels per memory chip also has a minor impact on how multi-channel "clamshell" mode works for higher capacity memory configurations. Whereas GDDR6 accessed a single memory channel from each chip in a clamshell configuration, GDDR7 will access two channels – what JEDEC is calling two-channel mode. Specifically, this mode reads channels A and C from each chip. It is effectively identical to how clamshell mode behaved with GDDR6, and it means that while clamshell configurations remain supported in this latest generation of memory, there aren't any other tricks being employed to improve memory capacity beyond ever-increasing memory chip densities.

On that note, the GDDR7 standard officially adds support for 64Gbit DRAM devices, twice the 32Gbit max capacity of GDDR6/GDDR6X. Non-power-of-two capacities continue to be supported as well, allowing for 24Gbit and 48Gbit chips. Support for larger memory chips further pushes the maximum memory capacity of a theoretical high-end video card with a 384-bit memory bus to as high as 192GB of memory – a development that would no doubt be welcomed by datacenter operators in the era of large language AI models. With that said, however, we're still regularly seeing 16Gbit memory chips used on today's memory cards, even though GDDR6 supports 32Gbit chips. Coupled with the fact that Samsung and Micron have already disclosed that their first generation of GDDR7 chips will also top out at 16Gbit/24Gbit respectively, it's safe to say that 64Gbit chips are pretty far off in the future right now (so don't sell off your 48GB cards quite yet).

For their latest generation of memory technology, JEDEC is also including several new-to-GDDR memory reliability features. Most notably, on-die ECC capabilities, similar to what we saw with the introduction of DDR5. And while we haven't been able to get an official comment from JEDEC on why they've opted to include ECC support now, its inclusion is not surprising given the reliability requirements for DDR5. In short, as memory chip densities have increased, it has become increasingly hard to yield a "perfect" die with no flaws; so adding on-chip ECC allows memory manufacturers to keep their chips operating reliably in the face of unavoidable errors.

This figure is reproduced, with permission, from JEDEC document JESD239, figure 124

Internally, the GDDR7 spec requires a minimum of 16 bits of parity data per 256 bits of user data (6.25%), with JEDEC giving an example implementation of a 9-bit single error correcting code (SEC) plus a 7-bit cyclic redundancy check (CRC). Overall, GDDR7 on-die ECC should be able to correct 100% of 1-bit errors, and detect 100% of 2-bit errors – falling to 99.3% in the rare case of 3-bit errors. Information about memory errors is also made available to the memory controller, via what JEDEC terms their on-die ECC transparency protocol. And while technically separate from ECC itself, GDDR7 also throws in another memory reliability feature with command address parity with command blocking (CAPARBLK), which is intended to improve the integrity of the command address bus.

Otherwise, while the inclusion of on-die ECC isn't likely to have any more of an impact on consumer video cards than its inclusion had for DDR5 memory and consumer platforms there, it remains to be seen what this will mean for workstation and server video cards. The vendors there have used soft ECC on top of unprotected memory for several generations now; presumably this will remain the case for GDDR7 cards as well, but the regular use of soft ECC makes things a lot more flexible than in the CPU space.

This figure is reproduced, with permission, from JEDEC document JESD239, figure 152

Finally, GDDR7 is also introducing a suite of other reliability-related features, primarily related to helping PAM3 operation. This includes core independent LFSR (linear-feedback shift register) training patterns with eye masking and error counters. LFSR training patterns are used to test and adjust the interface (to ensure efficiency), eye masking evaluates signal quality, and error counters track the number of errors during training.

Technical matters aside, this week's announcement includes statements of support from all of the usual players on both sides of the isle, including AMD and NVIDA, and the Micron/Samsung/SKhynix trifecta. It goes without saying that all parties are keen to getting to use or sell GDDR7 respectively, given the memory capacity and bandwidth improvements it will bring – and especially in this era where anything aimed at the AI market is selling like hotcakes.

No specific products are being announced at this time, but with Samsung and Micron having previously announced their intentions to ship GDDR7 memory this year, we should see new memory (and new GPUs to pair it with) later this year.

JEDEC standards and publications are copyrighted by the JEDEC Solid State Technology Association.  All rights reserved.

Now well in the midst of executing its plan to divide itself into separate hard drive and NAND businesses, Western Digital today offered a fresh update on the state of that split, and what the next steps are for the company. With the eventual goal of dividing the company into two independent, publicly traded companies, Western Digital is reporting that they have made significant progress in key transactional projects, and they are also announcing their initial leadership appointments for the post-separation businesses.

Western Digital's separation, announced on October 30, 2023, aims to create two focused companies with distinct product lineups for hard drives and NAND flash memory, respectively, as well as NAND flash memory-based products. This move is expected to speed up innovation and introduce new growth opportunities, according to Western Digital. Meanwhile, with separate capital structures, operational efficiency of the two entities will be higher compared to the united company, the management of Western Digital claims.

Western Digital led the storage industry's consolidation by acquiring HGST, various SSD and flash companies in the early 2010s, and SanDisk in 2016 for NAND flash production. As a result, in late 2010s the company become a media-agnostic, vertically-integrated storage technology company. However, the company faced challenges in growing its revenue. The 3D NAND and SSD markets are highly competitive commodity markets, and as a result they tend to fluctate depending on supply and demand. Meanwhile, demand for HDDs is declining and offseting decreasing unit sales with 3D NAND-based products and nearline hard drives was challenging. Meanwhile, to avoid avoid competition with larger storage solutions providers like Dell, HPE, and IBM — which purchase Western Digital's HDDs, SSDs, and NAND memory — Western Digital had to divest its storage solutions, which presents additional challenges.

As a result, Western Digital's HDD and NAND businesses have acted largely independently since late 2020, when it became apparent that the combined company has failed to become bigger than the sum of Western Digital and SanDisk parts. So far, quite some progress has been made in preparing for the separation, including establishing legal entities in 18 countries, preparing independent financial models, and finalizing preparations for regulatory filings. As a result, the company remains on track to finish the split in the second-half of this year, according to Western Digital.

With regards to post-split leadership, David Goeckeler has been appointed as the chief executive designate for the NAND flash memory spinoff company. He expressed enthusiasm for the NAND business's potential in market growth and the development of new memory technologies.

"Today's announcement highlights the important steps we are making towards the completion of an extremely complex transaction that incorporates over a dozen countries and spans data storage technology brands for consumers to professional content creators to the world’s leading device OEMs and the largest cloud providers," said David Goeckeler, CEO of Western Digital. "I am pleased with the exceptional work the separation teams have done so far in creating a spin-ready foundation that will ensure a successful transition to independent, market-leading companies for our Flash and HDD businesses."

Meanwhile, Irving Tan, currently executive vice president of global operations, will assume the CEO role for the standalone HDD company, which will continue to operate under the Western Digital brand. It is unclear where Ashley Gorakhpurwalla, currently the head of WDC's HDD business unit, will end up, or if he'll even remain with the company at all.

"While both Western Digital's businesses will have the strategic focus and resources to pursue exciting opportunities in their respective markets once the separation is complete, the Flash business offers exciting possibilities with market growth potential and the emerging development of disruptive, new memory technologies," added Goeckeler. "I am definitely looking forward to what's next for the spinoff team."

Western Digital had unveiled the SanDisk Professional PRO-BLADE modular SSD ecosystem in mid-2022 to serve the needs of the professional market. Compact and sturdy NVMe drives (PRO-BLADE SSD Mag) swappable across discrete bus-powered enclosures (PRO-BLADE TRANSPORT), and also compatible with a multi-bay reader (PRO-BLADE STATION) have perfectly fit the requirements of multi-user / multi-site workflows in the content capture industry. Read on for a detailed look at the first-generation PRO-BLADE SSD Mags and the PRO-BLADE TRANSPORT enclosure. In addition to the evaluation of the performance consistency, power consumption, and thermal profile, an analysis of the internals is also included.

As Intel prepares to move its fabs into its new Intel Foundry business, it will change the way it reports results in the coming months. To discuss the company's long-term vision and give investors a better understanding of how Intel's business will move forward with Intel Foundry and Intel Products groups, Intel plans to host a webinar on segment reporting on April 2, 2024.

"The webinar will discuss the longer-term vision for the foundry business and the importance of establishing a foundry-like relationship between Intel Foundry, Intel's manufacturing organization, and Intel Products, its product business units, to drive greater transparency and accountability," the description of the event reads.

The company plans to submit an 8-K form, revising its past financial reports to align with a new reporting framework, before the upcoming investor webinar. Starting with Q1 FY2024, Intel will disclose its financial outcomes using this new reporting structure.

One of the things that Intel will touch upon at the webinar is the financial and market performance of the Intel Foundry division. These things may not impress. It is likely that initially, Intel Foundry's business will have high costs, and the majority of orders will come from Intel itself (i.e., a significant but still relatively low market share). Meanwhile, Intel Foundry has to invest in advanced fab tools to prep its fabs for 20A and 18A, which drives its costs up, and this likely means losses.

Yet, it will take some time before Intel Foundry obtains revenue streams from major customers, such as Microsoft or the U.S. military. IF's financial numbers and market share may still not impress immediately, but this is normal at this stage. This is perhaps what Intel will communicate and discuss at its upcoming webinar.

In fact, although Intel fully expects its 18A (1.8nm-class) fabrication process to be ahead of its rivals in terms of power, performance, and area (PPA), the company's chief financial officer reiterated at a conference this week that it does not expect to win the bulk of any large customer's chip orders with this technology.

"We probably will not win anybody's major volume [with] 18A," said David Zisner, CFO of Intel, at the Morgan Stanley Technology, Media, and Telecom Conference (via SeekingAlpha). "We will win some smaller SKUs, and that is all we need, to be honest with you. That will be very significant to us, even though it seems maybe marginal in the marketplace, particularly if we can collect enough of these customers [developing high-performance compute chips]."

Intel's 18A fabrication process builds upon the company's 20A manufacturing technology (a 2nm-class node) that introduces RibbonFET gate-all-around transistors and PowerVia backside power delivery network. In GAA transistors, horizontal channels are fully encased by gates. These channels are built using epitaxial growth and selective removal, enabling adjustments in width for enhanced performance or lower power use. As for the backside power delivery network (BS PDN), the technique moves power lines to the wafer's back, separating them from I/O wiring, which allows for making power vias thicker and reducing their resistance, which helps to both increase transistor performance and lower power consumption.

Both GAA transistors and BS PDN promise to offer significant performance and power efficiency enhancements, which is good for AI, HPC, and smartphone SoCs. Meanwhile, 18A promises a 10% performance per watt improvement over 20A and GAA innovations. Thus, it promises to be quite competitive compared to TSMC's N3B and N3P.

"When it comes to the high-performance compute part of the market, that is really where we are starting to see a lot of our uptake," said Zisner. "The particular aspects of 18A with PowerVia and RibbonFET, combined with our just legacy of experience on high-performance compute, I think, makes us a really compelling partner for customers that are in that space and want to develop products."

Intel's 18A was designed to be a major foundry node, and consequently, its process design kit (PDK) is now available and the production technology is compatible with third-party electronic design automation (EDA) and simulation tools. However, Intel itself does not expect this process to be used for high-volume products of third parties. Even Microsoft is currently only slated to produce one chip on Intel's 18A.

Intel Foundry is a newcomer to the contract chipmaking market. As a result, Intel is planning for a multi-generational effort to break into the market, as the company will need to earn the confidence and business of third-party customers. As this happens, Intel Foundry expects to gain market share and reach profitability.

Sources: Intel, SeekingAlpha

V-Color has launched several EXPO-certified DDR5 RDIMM memory kits for AMD's Ryzen Threadripper 7000 Pro and non-Pro platforms. The new RDIMM memory kits, which only come in an eight-DIMM configuration, will enable workstation users to push the limits on the WRX90 platform with frequencies up to DDR5-7200 and memory kit capacities up to a staggering 768 GB (8 x 96 GB).

These are your typical run-of-the-mill modules without the fancy heatsinks and flashy RGB lighting. The recipe for the RDIMMs revolves around a 10-layer PCB paired with SK hynix's DRAM chips. And as the Threadripper platforms are all one DIMM per channel (1DPC) designs, V-Color's octo-kits are intended to populate all the memory slots on the WRX90 motherboard in one go.

V-Color is offering their RDIMM kits in several capacities and frequencies, with kit capacities ranging from 128 GB (8 x 16 GB) up to 768 GB (8 x 96 GB), while clockspeeds start at DDR5-5600 and top out at DDR5-7200.

Typical for RDIMM kits, the maximum frequency will vary depending on the memory kit capacity. There are two factors to consider: binning costs and achieving stability at faster frequencies on higher capacities is more challenging for the processor. Ryzen Threadripper 7000 Pro and non-Pro chips officially support DDR5-5200 memory modules. Anything higher is overclocking; stability depends on the processor's integrated memory controller (IMC) quality. DDR5-7200 is only available on V-Color's 128 GB, 192 GB, and 256 GB memory kits. Meanwhile, the 512 GB and 768 GB memory kits top out at DDR5-6000.

The DDR5-5600 and DDR5-6000 memory kits are the only ones rated to run at a relatively modest 1.25 V. The higher-end ones require 1.40 V due to the higher frequency and tighter memory timings. The memory timings on V-Color's RDIMM memory kits are decent, though they're far from rivaling premium DDR5 mainstream memory kits. The DDR5-5600 memory kit has 36-38-38-38-80 timings, whereas the DDR5-6000 and DDR5-6400 memory flaunts 32-39-39-102 timings. At the same time, V-Color binned the DDR5-6600 and DDR5-6800 memory kits for 34-46-46-92 and the DDR5-7000 and DDR5-7200 memory kits for 34-43-43-102 and 36-46-46-112, respectively.

V-Color's RDIMM products are overclocked memory kits with a limited lifetime warranty. They come with AMD EXPO support to facilitate one-click memory overclocking. The memory kits are built specifically for the WRX90 platform but should work on Intel platforms (your mileage will vary, of course). Regarding the QVL, V-Color has validated the brand's overclocked RDIMMs on the Asus Pro WS WRX90E-Sage SE and the ASRock WRX90 WS Evo, motherboards that cost over $1,000.

The 128 GB DDR5-5600 memory kit is the most affordable out of the lot, with an MSRP of $1,049.99, whereas the 192 GB counterpart sells for $1,579.99. At the other end of the spectrum, the flagship 768 GB DDR5-6000 memory kit has an hefty $4,919.99 price tag. V-Color's RDIMM memory kits are up for pre-order on the company's online store, and the vendor will ship orders on March 15. The memory kits will be available worldwide through official distribution partners on the same date.

Today NVIDIA has brought variable refresh rate support to its GeForce Now cloud gaming service. The company initially promised variable refresh support on GeForce Now back in early January during CES, and has seemingly waited so that it could launch alongside GeForce Now Day Passes, which are also now available.

Variable refresh rate (VRR) technologies, including NVIDIA's own G-Sync, have been around for around a decade now, and allow a monitor to synchronize its refresh rate to the instantaneous framerate of a game. This synchronization prevents screen tearing, when two or more frames are present on a display at the same time. Without a VRR technology, gamers either have to tolerate the visual incongruity of screen tearing or enable V-Sync, which solves screen tearing by locking the framerate to the refresh rate (or a fraction thereof). VRR became popular because V-Sync added latency and could depress framerates due to it effectively being a framerate limiter.

Dubbed "Cloud G-Sync", NVIDIA touts not only a screen tearing-free experience for GeForce Now thanks to variable refresh rate support, but also lower latency thanks to “varying the stream rate to the client, driving down total latency on Reflex-enabled games.” Prior to VRR’s debut on GeForce Now, users either had to enable V-Sync in-game, enable a stream-level V-Sync setting that had the benefit of not locking the game framerate, or accept screen tearing. GeForce Now Ultimate members will also be able to pair VRR with Reflex-powered 60 FPS and 120 FPS streaming modes.

According to NVIDIA’s technical documentation, variable refresh rate support on GeForce Now can work with both Mac and Windows PCs hooked up to a VRR-capable monitor. This includes G-Sync monitors on Windows, as well as VESA AdaptiveSync/FreeSync monitors, HDMI 2.1 VRR displays, and even Apple ProMotion displays, such as the panels built into their recent MacBook Pro laptops. The biggest compatibility hurdle at this time is actually on the GPU side of matters; Windows machines need an NVIDIA GPU to use VRR with GeForce Now. Intel and AMD GPUs are "not supported at this time."

Although G-SYNC originally came out in 2013 and GeForce Now has been available since 2015, the two never intersected until now. It’s not clear why NVIDIA waited so long to bring G-Sync to GeForce Now; the company’s original announcement merely states “newly improved cloud G-SYNC technology goes even further,” implying that it wasn’t possible before but doesn’t exactly explain why.

Taiwan External Trade Development Council (TAITRA), the organizer of Computex, has announced that Pat Gelsinger, chief executive of Intel, will deliver a keynote at Computex 2024 on June 4, 2024. Focusing on the trade show's theme of artificial intelligence, he will showcase Intel's next-generation AI-enhanced products for client and datacenter computers.

According to TAITRA's press release, Pat Gelsinger will discuss how Intel's product lineup, including the AI-accelerated Intel Xeon, Intel Gaudi, and Intel Core Ultra processor families, opens up new opportunities for client PCs, cloud computing, datacenters, and network and edge applications. He will also discuss superior performance-per-watt and lower cost of ownership of Intel's Xeon processors, which enhance server capacity for AI workloads.

The most intriguing part of Intel's Computex keynote will of course be the company's next-generation AI-enhanced products for client and datacenter computers. At this point Intel is prepping numerous products that pose a lot of interest, including the following:

• Arrow Lake and Lunar Lake processors made on next-generation process technologies for desktop and mobile PCs and featuring all-new microarchitectures;
• Granite Rapids CPUs for datacenters based on a high-performance microarchitecture;
• Sierra Forest processors with up to 288 cores for cloud workloads based on codenamed Crestmont energy-efficient cores;
• Gaudi 3 processors for AI workloads that promise to quadruple BF16 performance compared to Gaudi 2.
• Battlemage graphics processing units.

All of these products are due to be released in 2024-2025, so Intel could well demonstrate them and showcase their performance advantages, or even formally launch some of them, at Computex. What remains to be seen is whether Intel will also give a glimpse at products that are further away, such as Clearwater Forest and Falcon Shores.

Marvell this week introduced its new IP technology platform specifically tailored for custom chips for accelerated infrastructure made on TSMC's 2nm-class process technologies (possibly including N2 and N2P). The platform includes technologies essential for developing cloud-optimized accelerators, Ethernet switches, and digital signal processors.

"The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure," said Sandeep Bharathi, chief development officer at Marvell. "Our partnership with TSMC on our 5nm, 3nm and now 2nm platforms has been instrumental in helping Marvell expand the boundaries of what can be achieved in silicon."

The 2nm platform is built on Marvell's extensive IP portfolio, which includes advanced SerDes capable of speeds beyond 200 Gbps, processor subsystems, encryption engines, SoC fabrics, and high-bandwidth physical layer interfaces. These IPs are crucial for developing and producing a range of devices, such as custom compute accelerators and optical interconnect digital signal processors. These are becoming common building blocks for AI clusters, cloud data centers, and other infrastructures supporting machines used for AI and HPC workloads.

While these IPs are vital for a variety of processors, DSPs, and networking gear, developing them from scratch—especially for TSMC's 2nm-class process technologies that rely on gate-all-around Nanosheet transistors—is hard, time-consuming, and sometimes inefficient, both from a die space and economics point of view. This is where Marvell's IP portfolio promises to be very useful.

Marvell does not outright say that its TSMC 2nm-certified platform is silicon-proven, but given the fact that TSMC has been working with IP providers over N2-compatible IPs for quite some time, it is reasonable to expect that at least some of Marvell's popular IPs are.

"We take a modular approach to semiconductor design R&D, focusing first on qualifying foundational analog, mixed-signal IP and advanced packaging that can be used across a broad spectrum of devices," Bharathi said. "This allows us to bring innovations such as process manufacturing advances faster to market."

Meanwhile, Marvell is not part of TSMC's Open Innovation Platform and OIP's IP Alliance, so it is unclear whether the company's N2-compatible IPs will be part of TSMC's TSMC9000 IP program, which greatly simplifies IP choices for chip designers.

"TSMC is pleased to collaborate with Marvell in pioneering a platform for advancing accelerated infrastructure on our 2nm process technology," said Kevin Zhang, senior vice president of business development at TSMC. "We are looking forward to our continued collaboration with Marvell in the development of leading-edge connectivity and compute products utilizing TSMC's best-in-class process and packaging technologies."

Source: Marvell

Once the domain of external, bus-powered hard drives, these days the market for external storage has been almost completely consumed by portable SSDs. Rapid technological advancements in NAND flash technology (including the advent of 3D NAND) has allowed their capacity to eclipse 2.5-inch HDDs, all the while multiple improvements in host interface speeds (such as the move from USB 2.0 to 3.0, and onwards to 3.2 Gen 2 / Gen 2x2 / USB4) has made portable SSDs faster and more reliable than the hard drives they replace. All of which has helped to make portable SSDs the go-to solution for external storage, both big and small.

For our latest storage buyer's guide, we've rounded up some of the best portable SSDs we've looked at in the past couple of years. What's hot, what's not, and what's a good deal while still offering reasonable performance? We break that down and make our picks for the best portable SSDs on the market today.

SiPearl, a processor designer supported by the European Processor Initiative, is about to start shipments of its very first Rhea processor for high-performance computing workloads. But the company is already working on its successor currently known as Rhea-2, which is set to arrive sometimes in 2026 in Exascale supercomputers.

SiPearl's Rhea-1 datacenter-grade system-on-chip packs 72 off-the-shelf Arm Neoverse V1 cores designed for HPC and connected using a mesh network. The CPU has an hybrid memory subsystem that supports both HBM2E and DDR5 memory to get both high memory bandwidth and decent memory capacity as well as supports PCIe interconnects with the CXL protocol on top. The CPU was designed by a contract chip designer and is made by TSMC on its N6 (6 nm-class) process technology.

The original Rhea is to a large degree a product aimed to prove that SiPearl, a European company, can deliver a datacenter-grade processor. This CPU now powers Jupiter, Europe's first exascale system that uses nodes powered by four Rhea CPUs and NVIDIA's H200 AI and HPC GPUs. Given that Rhea is SiPearl's first processor, the project can be considered as fruitful.

With its 2^nd generation Rhea processors, SiPearl will have to develop something that is considerably more competitive. This is perhaps why Rhea-2 will use a dual-chiplet implementation. Such a design will enable SiPearl to pack more processing cores and therefore offer higher performance. Of course, it remains to be seen how many cores SiPearl plans to integrate into Rhea 2, but at least the CPU company is set to adopt the same design methodologies as AMD and Intel.

Given the timing for SiPearl's Rhea 2 and the company's natural with to preserve software compatibility with Rhea 1, it is reasonable to expect the processor to adopt Arm's Neoverse V3 cores for its second processor. Arm's Neoverse V3 offer quite a significant uplift compared to Neoverse V2 (and V1) and can scale to up to 128 cores per socket, which should be quite decent for HPC applications in 2025 – 2026.

While SiPearl will continue developing CPUs, it remains to be seen whether EPI will manage to deliver AI and HPC accelerators that are competitive against those from NVIDIA, AMD, and Intel.